[SI-LIST] Re: Reference for DDR3 signals
- From: Seunghyun Hwang <ehshehsh@xxxxxxxxxx>
- To: carson.au@xxxxxxxxx
- Date: Wed, 14 May 2014 14:56:16 -0700
Hi Carson,
You can find the aforementioned paper on below address.
https://drive.google.com/file/d/0B8EFmmMvmr2TR0RmWEVMa3hBS1E/
Thanks,
Eddy
On Thu, May 8, 2014 at 5:02 PM, Carson Au <carson.au@xxxxxxxxx> wrote:
> Hi Liuping,
> Is the paper "Mixed-Reference for Optimal Cost & Performance in High-Speed
> Memory Interface" freely available?
>
> Regards,
> Carson Au
>
>
> On Thu, May 8, 2014 at 8:33 PM, Luping Liu <liewluping@xxxxxxxxx> wrote:
>
> > Hi Syed:
> > For short answer, I suggest you take all the signals reference to
> > GND, if not enough layers , you can put Add/cmd reference to VDDQ, but
> keep
> > the DQ/DM refer to GND. Below are some information about this topic.
> >
> > 1. The latest paper on this work is 'Mixed-Reference for Optimal Cost &
> > Performance in High-Speed Memory Interface' ,Seunghyun Hwang etc.,
> > Nvidia,Designcon 2014. It compares the mixed power/ground reference with
> > all ground reference case, the former may add more crosstalk and
> > non-negligible power noise coupling to trace. Some may suggest that
> > sandwich like power/ground reference may have less SSN noise, consider
> > both 0-1 and 1-0 switch, but I haven't seen any simulation or measurement
> > data to support this .
> >
> > 2. In my opinion, it is not just a reference plane chose problem ,but a
> > stackup design or a system design problem, if your design is not cost
> > sensitive , then chose all ground reference, if cost is make sense,
> then
> > we should think both the reference plane and the power integrity problem,
> > which means ,you can use mixed reference ,but don't forget the
> power/ground
> > pair need of the IO power, especially at your high data rate. the G S
> S P
> > G like stackup may better than the G S G S P type with careful
> dielectric
> > thickness design.
> >
> > 3.Besides the DIMM board reference plane check, both the controller and
> the
> > memory chip package reference plane should be checked as a design input
> > too.
> >
> > Hope these can helpful to you.
> >
> > Good luck.
> > LIU Luping
> >
> >
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