Just one minor clarification.
The 2016 DesignCon paper was by far not the origin of the discovery and
probably was not the first publication on the subject.
We experienced this problem years earlier exactly on a crystal
oscillator with clamshell layout. It is still true though that
dependent on component size and additional layout and placement
constraints, there are many situations when the clamshell design is the
best, as long as there is no strong aggressor field nearby.
Best regards,
Istvan Novak
Samtec
On 3/3/2022 5:52 AM, Alexandre Desnoyers wrote:
Hi Istvan and Peter.------------------------------------------------------------------
The best explanation for the DC-DC loop problem is presented in a paper
from Istvan on his website:
http://www.electrical-integrity.com/Paper_download_files/DC16_SLIDES_Mid-FrequencyNoiseCouplingBetweenDC-DC_Kocubinski.pdf
see slide 14.
...and yes, this problem was discovered for a PCIe Gen3 link, but it's
100% certain that you'll have the same or worst problem if you did the
same layout and had a crystal with vias nearby.
But as everyone said: it depends....
Best regards to both of you,
Alexandre Desnoyers
Electronic Design Engineer
Qtechnology A/S
Emdrupvej 28A, 2.sal - 2100 København Ø - Denmark - www.qtec.com
Istvan Novak (istvan.novak) wrote:
Hi Peter,------------------------------------------------------------------
Imagine a PCB design where you have multiple circuits with clamshell
design: one would be the oscillator and maybe another a DC-DC converter,
where you place input and output capacitors and active devices/inductors
in a clamshell form. In this scenario the via-loop of the oscillator
becomes the victim and the via-loop at the DC-DC converter acts like an
aggressor. You have multiple loops, all vertical, so they will be
magnetically coupled unless you orient them precisely in an orthogonal
fashion. The power converter noise will show up as jitter on the
oscillator output. Whether it is an issue, of course, still depends on
many other things; it could be OK or it could be a problem. And this
example is not purely theoretical; reference clocks failed jitter spec
because of this.
Best regards,
Istvan Novak
Samtec
On 3/2/2022 1:32 PM, contact@xxxxxxxxxxxxxxxx wrote:
Dear Istvan,------------------------------------------------------------------
Thank you for your detailed and insightful response. Oh your example is
spot on: it is a clamshell design, and space-constrained too! :)
it is susceptible to noise pickup from loopsI'm not a 100% sure if I understand what you mean here. Could you please
of power-ground via pairs in the same board.
point me in the right direction?
Many thanks,-
Peter
On 2022-03-02 03:50, Istvan Novak wrote:
Hi Peter,------------------------------------------------------------------
Of course individual recommendations may be wrong, but there is a
simple and generic reason explaining and justifying why
recommendations may be different. Crystals and crystal oscillators
are sensitive circuits, and even though the high Q of the crystal
helps to suppress noise, an oscillator with very tight jitter
specification could be very sensitive to offending noise from very
different sources. So simply the nature of the surrounding system may
drive people to different ways to minimize noise-induced jitter. Just
one example: why you may see suggestions to lay out all critical
components around the crystal on the same side of the board. Using
clamshell type designs, placing components on the top and bottom of
the board connected by vias will achieve smaller total footprint and
more compact layout, but it is susceptible to noise pickup from loops
of power-ground via pairs in the same board. And it is a real risk
and we wont see the problem if we create a test board with only the
oscillator; we need everything else around it in the final
application.
So as the saying goers: it depends. The best approach is to be aware
of the potential problems and select a solution that will result in a
working solution.
Regards,
Istvan Novak
Samtec
On 2/28/2022 12:17 PM, contact@xxxxxxxxxxxxxxxx wrote:
Dear Fellows,
Could anybody please recommend any half-sensible AppNotes/Design
Guides
for placing a 25MHz crystal on a PCB? I've done a quick search and a
read a few recommendations but I'm really dubious --skeptical, even--
about the validity of their content. All of them seem to repeat stuff
along these lines:
* absolutely no vias
* no right-angle bends (my favourite)
* total symmetry of everything
* XI should be closer to device pin than XOUT (so much for
symmetry)
* single-point ground
* put the crystal on the same side as the device using it
My problem is that none of the recommendations take into account the
number of layers, their arrangement or their spacing. I'd have no
problem putting the crystal and the load caps on the opposite side of
the device and connect them with vias. Why? Because I have more space
and fewer noisy components down there and my parasitics can be kept
way
lower than by keeping everything on the same layer and using traces
for
connections.
I've reached a point in my career where I have learnt not to trust
AppNotes (except a select few) but haven't quite got far enough where
I
can always follow my own lead ('my own lead' == hundreds of hours of
reading select literature and papers). Sometimes I need a little
reassuring push... in either the forward or backward direction :)
Many thanks for any and all, who chip in.
PS. is this is considered a noob question for the level of this list,
just let me know and I'll remove it.
Best wishes,-
Peter
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