[SI-LIST] Re: Random behaiour of Virtex 4 FPGA
- From: "Mikhail Matusov" <matusov@xxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 12 Feb 2008 12:35:17 -0500
Hi Vijayan,
Are you using MGTs by any chance? If you power up every MGT in this part as
Xilinx recommends to prevent them from damage due to the static behaviour
anomaly, your power supply will see huge load...
Also, have you tried more than one card? Have you asked your PCB assembler
to do an X-ray of how the FPGA mounted?
Finally, a better place for this kind of questions would be the
comp.arch.fpga newsgroup.
/Mikhail
> Hi all,
> I am using Virtex 4 FPGA (XC4VFX100) in our application. In this, we find
> some random behaiour of FPGA.
>
> Whenever the bit file is loaded into the FPGA, there is a drop in core
> voltage(power module getting shutdown).Bit file gives such random
> behaviour uses particular three banks for its logic. Here we thought like
> this, it may be due to any internal damage in FPGA IOBs around that three
> banks.
>
> Here is the few points added,
>
> * We tried with a bit file that has high logic utilization (logic is not
> on that faulty banks. it uses other banks). It works fine.
> * Also we tried some other bit files with low logic utilization using that
> banks is working properly (power won't disturbed).
> * Whatever signals from that faulty banks are not shorted with VCC/GND. We
> probed it.
> * Good core voltage power solution.
>
> Pls suggest me the solution to identify the exact source of that random
> behaviour.
>
> Regards,
> Vijayan Sivamani
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