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Arpad
============================
From: Muranyi, Arpad
Sent: Thursday, August 27, 2020 12:33 PM
To: 'si-list@xxxxxxxxxxxxx' <si-list@xxxxxxxxxxxxx>
Cc: 'Ryan Lott' <ryan.lott.ee@xxxxxxxxx>
Subject: RE: RLC in IBIS models
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Arpad
========================
From: Muranyi, Arpad
Sent: Thursday, August 27, 2020 12:18 PM
To: si-list@xxxxxxxxxxxxx
Cc: Ryan Lott <ryan.lott.ee@xxxxxxxxx>
Subject: RE: RLC in IBIS models
Adnan,
The IBIS specification does NOT define how an EDA tool should implement these
RLC
package models. Some tools may use a PI structure (where the capacitance value
is
divided in half and two capacitors are used on each side of the series RL).
Some tools
may use a “T” structure, and some tools convert these to a T-line (distributed)
equivalent
(using Z and TD derived from LC).
If you want to make sure the simulator does exactly what you want, you should
use the
[Define Package Model] keyword and its [Pin Numbers] keyword using the lumped
representation (L=0) for each element. That syntax will tell the EDA tool
exactly what
order they should use the R L C elements in the netlist.
But you could probably make a better model with the new Interconnect Modeling
syntax in IBIS v7.0. Did you consider using that?
Thanks,
Arpad
======================================================================
From: Yassin, Adnan [mailto:adnan.yassin@xxxxxxxxx] ;
Sent: Thursday, August 27, 2020 12:01 PM
To: Yassin, Adnan <adnan.yassin@xxxxxxxxx>; Muranyi, Arpad
<Arpad_Muranyi@xxxxxxxxxx>; si-list@xxxxxxxxxxxxx
Cc: Ryan Lott <ryan.lott.ee@xxxxxxxxx>
Subject: RE: RLC in IBIS models
Follow up question:
The order of R_pin/L_pin/C_pin in my care is very critical; is
it something I can control in IBIS model? The snapshot below shows the order of
my components (it is important to have C_comp and C_dq0 separated by
R_dq0/L_dq0, not placed next to each other):
Thanks,
-Adnan
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf Of
Yassin, Adnan
Sent: Wednesday, August 26, 2020 8:54 PM
To: Arpad_Muranyi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Cc: Ryan Lott <ryan.lott.ee@xxxxxxxxx>
Subject: [SI-LIST] Re: RLC in IBIS models
Thanks Arpad and Ryan for your detailed responses. It is clear now. 😊
-Adnan
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf Of
Muranyi, Arpad
Sent: Wednesday, August 26, 2020 6:40 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: RLC in IBIS models
Adnan,
EBD was originally conceived for memory modules. As such, the IBIS models on
those modules would be packaged devices, in other words the package model in
.ibs file would be retained.
So you would end up with the board description in the EBD file's [Path
Description] keywords, followed by the IBIS package model and then the buffer
[Model].
Nothing prevents you to use EBD for multi-chip modules. In that case the "PCB"
becomes the package, and the IBIS files become the dice. Usually people would
zero out the package in that case, because the die would be bare-die, but you
can keep the IBIS package if you like and that way you can have additional
"parasitics" between the package and the die, such as RDL, or similar. You can
use any of the package keywords in the IBIS file for that purpose.
In short, the package model in the IBIS components are retained, even if they
are invoked from an EBD file.
I hope this helps,
Arpad
============================================================================
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Yassin, Adnan
Sent: Wednesday, August 26, 2020 7:59 PM
To: si-list@xxxxxxxxxxxxx
Cc: Yassin, Adnan <adnan.yassin@xxxxxxxxx>
Subject: [SI-LIST] RLC in IBIS models
Hello,
I use EBD with IBIS model in my simulation. I have a case where I need to add
extra RLC between the package (EBD) and die pads (IBIS), and I was wondering if
I can use R_pin, L_pin & C_pin keywords in IBIS model to represent this
additional RLC! Does EBD model take complete precedence so RLC in IBIS are
totally ignored? If yes, is there a way to represent this extra RLC?
Thanks,
-Adnan
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