[SI-LIST] REPOST: SI Question 1 of 3: "Quiet" lines over split in ground plane
- From: "John-Paul Coetzee" <jpcoetzee@xxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 31 Oct 2005 09:32:23 -0000
Reposted to try and make the diagram clearer!
I am working on a telecoms design with Analog and Digital areas. The =
whole unit is inside a thick metal box, with the PCB bolted and grounded =
to the chassis across the board. Various parts of the PCB are also =
further isolated by slots in the ground and power planes and also by =
walls bolted to exposed ground plane on the top and bottom of the board.
Here is an ASCII picture of small part of the board showing a digital =
area, analog area, the slots isolating those areas and the soild metal =
wall. You will only be able to see this picture properly in monospaced =
font
There are 3 SPI serial data and clock lines crossing into the analog =
zone. These are only active in the first few seconds after power-up =
after which they are held low.
What are the risks of these "quiet" signals crossing the slot?
| ######### D I G I T A L G R O U N D
| #########
| +-------+######### +-----------------------
| | |######### | =20
| | |######### | S L O T =20
| | |### ### | =20
| | S |### W ### +-----------------------
| | |### ### =20
| | L |### A ### =20
| | |### ###
| | O |### L ###
| | |### ###
| | T |### L ### A N A L O G G R O U N D
| | |### ###
| | |#########
| | |#########
| --------------------#########------------->------- SPI Clock
| | |#########
| --------------------#########------------->------- SPI Data
| | |#########
| --------------------#########------------->------- SPI LE
| | |#########
| | |#########
| | |#########
| | |#########
| | |#########
| +-------+#########
| #########
| #########
| #########
+----------------------------------------------------------------
--
JP Coetzee (was JP Nicholls) / jpcoetzee@xxxxxxxx
Digital Design Engineer
Powerwave UK Ltd
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