[SI-LIST] Re: Questions about interplane capacitance
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Joel Brown <joel@xxxxxxxxxx>
- Date: Wed, 05 Mar 2008 17:53:25 -0800
Joel,
1. The frequency at which plane capacitance dominates over bypass cap
impedance is approximately: F = 1/(2pi(Lbypass*Cplane)^0.5). If for
example you are using 4 mil planes then with no perforation, you've got
55pF in your 0.25"sq. Lspread depends on the thickness of the plane and
the IC power pin pattern. For a 4mil dielectric and an IC with a
healthy number of power pins it is typically somewhere between 10pH and
50pH ( usually leaning towards 50pH ). The point of diminishing returns
for the bypass caps is where Lbypass = Lspread. So, you get bang for
your buck out of the bypass caps down to 10pH - 50pH mounted
inductance. The resulting PRF is well over 1GHz.
2. It depends on the application as indicated above. The way that this
extends to systems with multiple ICs is that the plane area that is
exclusive to a given IC is the plane area that you should be calculating
PRF against. So, if you've got BGA's on a 2"x2" pitch, you've got a
little less than 4"sq of plane that "belongs" to each IC. In 4 mil
dielectric that's 0.9nF. For spreading plus bypass inductance in the
20pH - 100pH range, that sets the PRF between 500MHz and 1GHz. If you
use thin dielectric, you can either yield lower impedance to each IC, or
use fewer capacitors for the same nominal maximum impedance which will
then occur at a lower frequency. There are six things that you can do
to reduce the number of bypass caps needed in a design:
1) Design using the right metrics. Over designing or improper design
costs a lot of money. The idea behind tools like Sigrity's PI Optimizer
is to avoid over-design that often results from ad-hoc methods.
2) Use a stack-up optimized for power delivery. Putting the first plane
cavity in PCB layers 2/3 instead of 5/6 improves capacitor mounted
inductance by 1.5:1 or more, reducing the number of caps needed
commensurately.
3) Use low inductance caps. Connected to planes up high, gains of 4:1
are readily achievable.
4) Use a low inductance attachment scheme with your caps. How much the
via pattern dominates depends on how long the vias are and what kind of
cap you are using. A poor mounting / via attachment scheme just means
you have to buy more caps. Locating a cap on the far side of a 125mil
PCB increases mounted inductance 5:1 or more.
5) Use thinner dielectric. Using 1mil material instead of 2mil material
for the planes reduces the number of capacitors needed to track the same
total inductance as seen by the IC by about 1.5:1. As designs shrink,
thinner and higher eR dielectrics gain back capacitance.
6) Add area fill to unused space.
Of all of the measures, 1), 2), 4), and 6) can be had for the cost of
design effort, and/or tools. 2) puts pre-preg between signals and
planes. If your fabricator(s) have trouble consistently pressing panels
then it will increase your trace impedance variation. My answer is use
a better fabricator. But if you want to fabricate with a back-water
shop and your design has little tolerance for trace impedance variation,
it may be a consideration.
6) Is cheap and effective where you can use it. In Lee's book "Right
the First Time, Volume 1" Lee demonstrates a case where simply adding
area fills fixed an emissions problem.
3) and 5) both trade eliminating a bunch of bypass caps against more
expensive caps, or higher laminate cost. Eliminate enough costly
capacitor placements and these measures more than pay for themselves,
not to mention what they can do for real-estate. For the same amount of
parts / material 2), 3), 4), and 5) can all improve performance.
Samtec's PowerPoser(tm) pretty much uses all of these measures.
A closing caution on PRF. Both impedance magnitude and phase change
dramatically around the PRF. If the PRF occurs within your signal
frequency range, ( these days it usually does ) you are well-served to
damp it. There are several methods to do that.
Best Regards,
Steve.
Joel Brown wrote:
> Interplane capacitance is frequently cited as the only effective bypass
> capacitance on a PCB at frequencies above 200 MHz.
> I am currently working on a design which brings up some questions regarding
> interplane capacitance.
>
> 1. Power planes normally carry "standard" voltage rails that are used
> throughout a board such as +5V and +3.3V.
> High speed ICs usually have core voltages that are local to the IC and are
> provided by a local regulator which converts the standard rail to the core
> voltage (example 3.3 to 1.8V).
> The local core voltage is distributed on a plane area that is local to the
> IC and therefore is small in area (0.25 sq in or less) which results in a
> very small amount of interplane capacitance.
> Is this very small amount of capicitance effective for bypassing the IC? I
> am sure it depends somewhat on the current waveform being drawn by the IC
> but this can only be estimated because semiconductor manufacturers do not
> provide current consumption profile as a function of frequency. To make
> matters worse, some ICs have several different VCC pins which the
> manufacturer recommends connecting to separate networks of bypass caps and
> ferrite beads. This cuts the power distributuion up even more resulting in
> less (practically zero) interplane capacitance. It is somewhat ironic that
> the the voltages such as +5V and +3.3V which are required at points across
> the whole board and therefore have the most interplane capacitance are also
> the voltages which have least requirement for interplane capacitance because
> they do not directly supply high speed rails.
>
> 2. There has been a lot of emphasis on reducing the mounted inductance of
> bypass capacitors. Even with this reduced inductance they are still only
> effective up to several hundereds of MHz at which point the interplane
> capacitance becomes the only bypass capacitance mechanism. However there is
> inductance between the connection of the IC to the planes. This inductance
> consists of vias and package inductance. I did look for some numbers for
> package inductance and did not find much, it seems to be a closely held
> secret. Also it is unknown how much bypass capacitnace is internal to the IC
> package. Just for example if we assume 250pH for the vias and 500 pH for the
> package, then the impedance at 500 MHz would be 2.36 Ohms. This seems rather
> high for the interplane capacitance to be of much benefit.
>
> In summary how much interplane capacitance is needed to be beneficial, and
> why is it beneficial given the inductance in the vias and package?
>
> Thanks - Joel
>
>
>
>
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