[SI-LIST] Re: Question on split termination

From: "Dr. Howard Johnson" <howiej@xxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Wed, 27 Mar 2002 07:59:56 -0800
Dear Nianqing,

Apparantly your driver can't source enough current
to drive the impedance of the end terminator (or the
line to which it is connected).

You can compute directly from your datasheet
the smallest-valued end-termination that your
driver can safely drive, while meeting V(OH) and V(OL)
on every edge, assuming a perfect bias voltage
in the split termination. That number
(which I call ZMIN) is determined thus:

 ZMIN = (V(OH)-V(OL))/(I(OH)-I(OL))

Note in the above expression the denominator
is the spread between the high and low
output currents. For most chips, I(OH) is
positive and I(OL) is negative, so the
spread is actually the sum of the magnitudes.
For example, a gate which can source 20 mA
and sink 40 mA has a spread of (20 - (-40)) = 60 mA

Once you've determined ZMIN for your driver,
try an end termination with two resistors each
equal to twice ZMIN.

If ZMIN exceeds your line impedance there will be
some unavoidable ringing, but that's the best you
can do with an end termination given your driver
and line impedance.

You should at least get a full logic swing in
the steady-state condition after the line has
stabilized.

The next step is to carefully examine the exact
high and low logic levels to see that you are
meeting V(OH) and V(OL). With a symmetrical split
termination and ordinary CMOS logic (which pulls
harder in the low direction that when going high)
you will likely see that you are beating the
V(OL) number while not quite making V(OH). Tweak
the ratio of the two resistors (keeping the
parallel combination the same) to raise their
effective thevenin-equivalent bias point, thus
raising the DC level of the whole circuit. This
procedure should allow you to tune in the performance
to meet both V(OH) and V(OL).

The last step is the simplest: RAISE YOUR LINE IMPEDANCE.
This is done by shrinking the width of the line, or
by raising it up further above the nearest reference
plane. The closer you bring the line impedance to
the termination impedance the better your circuit will
work.

Good luck.

Best regards,
Dr. Howard Johnson, Signal Consulting Inc.,
tel +1 509-997-0505,  howiej@xxxxxxxxxx
http:\\sigcon.com  -- High-Speed Digital Design articles,
books, tools, and seminars




-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of nq_zhang
Sent: Tuesday, March 26, 2002 10:19 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Question on split termination



Hi,

I have an IO that is connected to an unterminated
transmission line.
Reading from Howard Johnson' book, I am trying to add
termination to
it at the far end. So I tried the split termination. However
when
I did that, if the buffer output is held high or low, the
output
at the far end is not vdd or 0. Can someone explain this for
me?
Is this normal? How should I make the output the right
value?


Thanks,
Nianqing


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[SI-LIST] Re: Question on split termination

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