[SI-LIST] Re: Question on ESD/EMC optimized GND Layout on PCB
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
- Date: Wed, 18 May 2011 01:12:26 -0700
This is the sort of subject that Doug Smith loves to talk about. You
should look through his site, because as usual: It depends.
Other comments inserted in-line
Steve.
On 5/18/2011 12:01 AM, Hermann Ruckerbauer wrote:
> Hello all,
>
> I'm searching for some information on optimized GND/shield
> implementation on the PCB for optimized ESD/EMC behavior and I hope that
> some of you could share a bit of your experience.
>
> Lets think about a PCB with an IO panel e. g. for Graphics and USB
> interfaces. The chassis is connected to the receptacles and these are
> connected to a Copper layer called "Chassis GND" on the PCB.
Comment: If such a layer covers the entire PCB, then we now have a
resonant cavity between that structure and the adjacent planes on the
PCB. That is an invitation to very bad things.
> The PCB
> itself does have a GND plane for referencing and current return for high
> speed signaling called "Digital GND".
>
> I have seen some designs that e. g. do connect the "digital GND" of the
> PCB directly to the Shielding/Chassis GND of the IO Connectors of a PC
> system board.
> But in some design guides I have seen some different implementation an
> optimized ESD/EMC Layout:
> Split "digital GND" of the PCB and the "Chassis GND" (GND connected to
> IO Panel and chassis) by a minimum distance and if possible make this
> "chassis GND" surrounding the hole PCB. Connect the "chassis GND" by a
> single connection to "Digital GND" and add AC coupling capacitors
> between Chassis and Digital GND. Connect this shield GND as good a
> possible to Chassis (e.g. by mounting holes).
Comment: Given a low-resistance DC connection, adding a bunch of
capacitors is an odd decision to make. It forms band-stop filters
defined by the inductance between the connection point(s) to any point
on the PCB, and the apparent capacitance of those coupling capacitors to
those same points. Like the parallel plane case, these filters unless
damped will tend to resonate when excited by ESD events, potentially
generating damaging voltages and currents.
> Maybe you have another opinion, or have any more detailed feedback on it.
>
> Questions would e. g:
> - Where should the connection between Shield GND plane of the IO Panel
> and digital GND plane should be made ? (As far as possible away from the
> IO Panel where the ESD event migth occur ?)- Should this connection be a
> trace on PCB (how wide ?), or e. g. via
> Resistor or even ferrite bead?
> - How wide the gap between the Chassis GND plane and Digital GND plane
> really needs to be ?
> - Is there any special requirement on the capacitors coupling Digital
> and Chassis GND (e. g. on ESD behavior).
>
> Thanks for any direct feedback and maybe some links for further reading ...
>
> thanks and regards
>
> Hermann
>
This depends on the construction of the system. Ultimately what you
want to insure is that the construction does not end-up creating
excessive common mode to differential mode conversion of discharged
energy. If a single point attachment were really the only point of
significant coupling, then the circuit common (Vss) could float on that
attachment, and the grounding system would not create mode conversion.
But life is rarely so simple. What you want to do is:
1. Provide as low an impedance path for unwanted discharges as possible
that does not include traverse through your operational circuitry.
2. Limit differential coupling between the intended discharge path, and
different parts of your operational circuitry.
When working out a strategy, one should be aware of the loops that form
at all frequencies where ESD has significant energy: IE at least
100kHz - 1GHz. Over that range, there are all sorts of opportunities
for parasitic coupling both capacitive and inductive between
structures. So what is going to work will vary quite a bit with the
particulars of the construction. I reiterate that building a big plate
capacitor between chassis and Vss is an invitation to nasty high Q
resonances that can be very destructive.
> EKH - EyeKnowHow
> Hermann Ruckerbauer
> www.EyeKnowHow.de
> Hermann.Ruckerbauer@xxxxxxxxxxxxx
> Veilchenstrasse 1
> 94554 Moos
> Tel.: +49 (0)9938 / 902 083
> Mobile: +49 (0)176 / 787 787 77
> Fax: +49 (0)3212 / 121 9008
>
>
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Steve Weir
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