[SI-LIST] Re: Question about SSTL Termination
- From: Witold Teller <Witold_Teller@xxxxxxxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 15 Jan 2002 16:08:46 -0800
Hi,
If you remove parallel termination resistors, the SSTL-2 driver behaves
similar to LVTTL one - it swings from 0 to VDDQ. The SSTL-2 driver
may have different current driving/sinking range than the LVTTL one.
Parallel termination resistors can be removed, and you may
get proper signal integrity with two serial termination resistors.
MICRON wrote apps note on serial termination.
You must simulate your circuit and select resistor values, or you may
get significant overshoots, driving current into clamping diodes
on the receiver, and possibly corrupting data. If it is bi-directional DATA
path, then both directions must be simulated.
Major difference between SSTL-2 and LVTTL is in receiver threshold.
SSTL-2 receiver checks edge at 50 % of supply voltage (Vref). LVTTL receiver
follows EIA/JESD8-5 or JESD8-B Standard, with wider transition voltage range.
Regards,
WT
-----Original Message-----
From: arsenault, brian [mailto:arsenault_brian@xxxxxxx]
Sent: Tuesday, January 15, 2002 10:50 AM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Question about SSTL Termination
Folks...
I'm working on a design within our company that is utilizing SSTL buffers.
We are working with a semiconductor vendor to add these buffers in as
selectable vs. LVTTL. Since we are in the definition stage, we also
requested that the termination needed for SSTL be built internal to the
device, reducing the number of external discrete components. As a note, we
are looking at SSTL2...
One question that came up was, 'Do we really need the pullup resistor (50
ohms to a Vt of 1.25V) or can we live with just the series terminator?'.
The simulations I have run with the pullup indicate a clean signal that
swings between 600mV and 1.8V. When I remove the pullup, the signal now
swings between 0V and 2.5V.
My question is, does this make sense? I have tried models from two
different vendors (Xilinx and LSI Logic). After reading the JEDEC spec on
SSTL, and also the vendor datasheets, I can't come up with an explaination.
Appreciate the help.
Brian
Brian Arsenault
Sr. Signal Integrity Engineer
EMC Corporation
Hopkinton, MA 01748
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