i think problem statement is not correct. it should be Pros&Cons of Bypass
and PLL MODE (not model) in PCIe clock buffer
In bypass mode, he is interested to feed the clock in SSC mode through
external clock generator source.
In PLL mode, he does not have SSC mode (but PLL can also have SSC mode, it
depends on your design and IP selection).
SSC feature will definitely give clock EMI reduction.
Both the clock mode (PLL & bypass) will be connected to final driving clock
IO buffer through MUX inside silicon.
Now his question is about pros & cons of SI/PI in both of these modes.
1. in bypass mode, high frequency clock needs to pass through all PCB,
package & silicon interconnects before it reaches to MUX. So interconnect
design needs to done very well. Inherent clock jitter will be less
assuming you have signal generator of good quality.
2. in PLL mode, power supply induced jitter is a major concern for any
PLL. So PLL related power integrity design needs to be isolated at all
level of silicon, package & PCB. PLL jitter will also depend on your Ref
clock quality and so many other factors.
Hope my understanding about the problem statement is correct.
Thanks & Regards
Sanjeev Gupta
www.sigintegrity-solutions.com
On Tue, Jul 12, 2016 at 1:21 PM, Tesla <emcesd@xxxxxxx> wrote:
It will much better that you describe what is your clock buffer. Made the
experts guess what you are using is wasting experts's precious time.
At 2016-07-12 13:48:33, "Chambers yin" <chambers.yin@xxxxxxxxx> wrote:
Hi SI experts,------------------------------------------------------------------
I am choosing a PCIe clock buffer, but confused on its working model -
bypass and PLL model. Can clock timing expert help me review it, and tell
me if I missed something or were wrong.
Bypass model:
- Pros: Support SSC
- Cons: long transport delay
PLL model:
- Pros: Short transport delay
- Cons: not support SSC
Besides these, which model will result into better SI performance, for
example, less jitter? Thanks for your reading this email.
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