[SI-LIST] Power Integrity Modeling and Design Seminar on 2/08/08, 1-4pm @ Sun, Menlo Park Bldg 12
- From: Derek Tsai <derek.tsai@xxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 28 Jan 2008 18:27:39 -0800
Folks,
We are honored to have Dr. Madhavan Swaminathan of Georgia Tech
to give us a free seminar on Power Integrity Modeling and Design.
Time: 2/08/08, 1-4pm
Place: Sun's Menlo Park Campus, Bldg 12 (MPK12)
Only 25 seats are available. First come first serve.
All attendees must be pre-registered so RSVP is needed.
(Reply to denise.odell@xxxxxxx only)
For More info see below or see the attached flyer.
Regards,
Derek
=========================================================
Power Integrity Modeling and Design for Semiconductors
and Systems
Power represents the major bottleneck in modern
semiconductors and systems. With transistor scaling,
Moore?s law has enabled the integration of millions of
transistors within an integrated circuit over the last two
decades. With lower gate capacitance and lower voltage,
faster transistors have resulted from one computer
generation to the next. However, increased transistor
integration has resulted in an increase in the current
supplied to the integrated circuit, thereby increasing
power. Managing the transient current supplied to
the integrated circuit at gigahertz frequencies is one
of the biggest challenges faced by the semiconductor
industry. With lowering of the supply voltage to the
transistors, dynamic variations in the power supply due
to current transients is becoming a major bottleneck.
The dynamic variation of the supply voltage, also called
power supply noise, delta I noise, or simultaneous
switching noise, is the subject of this seminar.
Managing power integrity is the process by which the
variations on the power supply of the transistors can
be maintained within a specified tolerance value. Noise
on the power supply can have a direct influence on the
speed of an integrated circuit, and hence supplying
clean power is a very important element in the design
of a computer system.
A power distribution network consists of interconnections
in the chip, package, and board that include decoupling
capacitors, ferrite beads, DC?DC converters,
and other components. Both the package and board
form a very critical part of the power distribution network
and have a major influence on power integrity
of the entire system. The focus of this seminar is on
power integrity in packages and boards.
Modeling is a very critical part of power integrity design.
Unlike Signal Integrity, modeling Power Integrity is not
straight forward. Moreover, Signal Integrity and Power
Integrity are inter-related and their infl uence on each
other cannot be ignored. This seminar covers various
elements of Power Integrity modeling with focus on real
world applications.
The seminar will be structured around the recently
published book entitled ?Power Integrity Modeling
and Design for Semiconductors and Systems?,
Power Integrity Modeling and Design
for Semiconductors and Systems
ISBN:0_13_615206_6, Prentice Hall, Nov. 2007 by the
speaker. The book comes with several practical examples
related to power integrity modeling that can be
reproduced using the free software that can be downloaded
from www.powerintegrity.net. Attendees interested
in purchasing the book will also obtain a special
discount from Prentice Hall.
Biography
Madhavan Swaminathan is the Joseph M. Pettit Professor
of Electronics in the School of Electrical and
Computer Engineering and Deputy Director of the
Microsystems Packaging Research Center, Georgia
Tech. He is the co-founder of Jacket Micro Devices,
a leader in integrated RF modules and substrates for
wireless applications (www.jacketmicro.com) and SoPWorX,
an EDA company specializing in CAD software
for System on Package applications (www.sopworx.
com). Prior to joining Georgia Tech, he was with IBM
working on packaging for supercomputers. He is the
author of more than three hundred journal and conference
publications, holds fi fteen patents, is author of two
books entitled ?Power Integrity Modeling and Design for
Semiconductors and Systems?, ISBN 0_13_615206_6.
Prentice Hall, Nov 2007 and ?Introduction to System on
Package?, MCGraw Hill, Mar. 2008. He has been honored
as an IEEE Fellow for his work on power delivery
for digital and mixed signal systems. He received his
PhD in Electrical Engineering from Syracuse University
in 1991.
Directions
Take 101 South from San Francisco to the Willow Road
East exit or take 101 North from San Jose area or take
Dumbarton Bridge (84) North from Fremont. Willow Road
will dead end at our campus; after going through the stop
light at 84 and Willow you will almost immediately turn left
(the building in front of you is #10) and follow around to
the second building #12. Tell the receptionist that you are
here for the seminar and to call Denise O?dell.
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