[SI-LIST] ‏‏RE: Power Integrity AC Analysis

  • From: Dudi Tash <dudi@xxxxxxxxxxxxxxxxx>
  • To: "balaseven@xxxxxxxxx" <balaseven@xxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Sat, 26 May 2012 20:52:50 +0300

Hi Bala,
The selection of the power supply components such as decoupling capacitors and 
creating a stackup to create a high bandwidth power supply, depends on the 
interfaces you have in your design. The bandwidth is calculated by using an 
empiric formula (based on a simplification of fourier series for square 
waveforms), and equals 0.35/rise time.
Suppose you have 1nsec rise time, the bandwidth shall be 350Mhz.
In order to provide a robust power rail supply, in this case, you should design 
your power supply to cover a constant TARGET IMPEDANCE for all over the 
frequency spectrum up to 350Mhz. In case there are faster rise times, the 
calculation should be done accordingly.
The power planes covers the higher range of the frequency spectrum, starting 
from about 700Mhz.
I hope this helps.
Dudi
________________________________________
þþîàú: þþsi-list-bounce@xxxxxxxxxxxxx [si-list-bounce@xxxxxxxxxxxxx] áùí bala 
[balaseven@xxxxxxxxx]
þþðùìç: þþùáú 26 îàé 2012 07:56
þþàì: si-list@xxxxxxxxxxxxx
þþðåùà: [SI-LIST] Power Integrity AC Analysis

Experts,
I have a question on Frequency Vs Impedance waveform in AC analysis and
need your help.On what basis we decide the frequency limit.Say
for example, if my VRM delivers 2.5V  IO to Ethernet Chip,is it enough if
my 'power plane impedance' under the limit(target impedance) upto 'Chips'
operating Frequency?Am i right? if not,Whats the role of
plane resonant frequency here?
--
bala


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