[SI-LIST] Re: Philosophical Question about SERDES Analyses
- From: "Beal, Weston" <Weston_Beal@xxxxxxxxxx>
- To: "kowal_edward2007@xxxxxxxxxxx" <kowal_edward2007@xxxxxxxxxxx>, SI LIST <si-list@xxxxxxxxxxxxx>
- Date: Thu, 5 Apr 2012 20:54:16 +0000
PCIe specification includes an eye mask constraint that a transmitter must meet
at the connector. Then it is required of the peripheral to ensure that it meets
its portion of the specification to be able to recover this attenuated signal.
Weston
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of edward kowal
Sent: Thursday, April 05, 2012 11:42 AM
To: SI LIST
Subject: [SI-LIST] Philosophical Question about SERDES Analyses
All,
I have been analyzing SERDES for some time, but have always been working for
organizations that are designing complete, end-to-end systems. Now I find
myself working with a firm that only designs and controls part of the signal
path (basically a SERDES on a daughtercard that will ultimately plug into a
backplane). I find myself confused as to how to proceed. I am fortunate in
that only two vendors make SERDES that would reside on the other (not the one I
am designing) end of the link. I suppose I need to make some serious
assumptions about the backplane and any interposing cables as well. Are
trace/cable lengths something that every appears in a standard (I seem to
remember that USB and DIsplayPort spec out maximum cable lengths), or is it
purely application dependent?
Specifically, this is in the context of SAS and PCI-E if that makes any
difference. I have yet to review these specs in detail, and I apologize if the
answers to my questions lay in them.
Your wisdom greatly appreciated in advance,
Ed
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