[SI-LIST] PECL termination - won't work ?
- From: "WALKER, Mark" <mark.walker@xxxxxxxxxxxxxxxxx>
- To: "'hariharan@xxxxxxxxxxx'" <hariharan@xxxxxxxxxxx>,"'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 14 Feb 2003 10:14:37 -0000
Hariharan, I would not claim to be an expert, especially given the calibre
of engineers who regularly enlighten the rest of us on this list, but I may
be able to make a useful contribution on this topic. However, if I am wrong,
hopefully we'll both learn from the real experts...
-- General thoughts on termination & use of ECL --
With ECL (or PECL, with Vcc at +5v & Vee at 0v/Gnd), a diff pair is really
two complimentary single ended signals, as opposed to a truly differential
signal, such as LVDS. Each PECL signal is normally terminated with Zo to Vtt
(where Vtt = Vcc - 2v), and Zo is usually 50R. If you don't have a separate
Vtt supply, you can, as you say, use a Y termination with adjusted values to
look like a pair of Zo resistors to a virtual Vtt. In this case I advocate
using a decoupler across the Vtt/Vee resistor, but its benefit is probably
negligible in most practical cases.
For ECL the termination to Vcc is actually doing two jobs. Firstly, it is
providing the path for current to flow: From power source & through the Vcc
pin of the driving IC, through it's output transistor (which I believe
approximates to 8R), out of the output pin(s) & along the transmission line,
down the termination resistor to Vtt & back to the power source. For the
edge speed of typical ECL, you have to assume the power source is the local
decoupling and make sure it is treated with care during layout. The current
through the IC's Vee pin(S) is constant, so concentrate decoupling on the
Vcc pins, whilst minimising loop area. Current from Vcc will only be
impulsive due to any mismatch in the timing between the Q & Q! edges and
while the transmission lines are being charged / discharged during the edge
propagation.
Differential termination is not normally used, with ECL, because it gives so
little benefit. Manufacturers quote device performance into 50R to Vtt. If
you wish use an alternative Zo, you should use IBIS models to check your
timing etc.
-- Thoughts on the specific design question --
I have had a quick look at the two devices being interfaced:
http://www.cypress.com/products/datasheet.cfm?partnum=CY7B951-SC
http://www.onsemi.com/pub/Collateral/MC100ELT23-D.PDF
The Cypress device data is only a brief features list, but if we assume it
is standard ECL then the termination scheme you suggest below will not work,
in my opinion. Bullet 7 on page 1 of the On-Semi part's datasheet mentions
internal input pulldown resistors, but I couldn't find a value quoted or
weather they are intended for pulling unused inputs safe (I suspect) or
signal termination. You don't quote a Zo for the traces joining the two
devices. It may be on the schematic as a net parameter, or implied in the
routing rules / stackup documents by the track width & its dielectric
spacing to the nearest plane, although this assumes you know which layer you
will be routing on. You should also see a diff_pair attribute to ensure that
the traces are correctly routed as a pair. You must not assume this will
magically happen on it's own!
Because of these unknowns it's difficult to see how the designer arrived at
the scheme you show below. I suggest the best course of action is to
challenge them to justify the scheme. In the discussion this challenge will
hopefully provoke it will probably transpire that they have made an invalid
assumption, possibly something to do with the signal being a clock &/+ a
misunderstanding of how ECL is terminated. There is always the outside
chance that the scheme is valid. In either case, having awoken our
collective curiosity, it is your job, hariharan, to report back with the
outcome.
Good luck,
Mark.
Design Engineer.
Stevenage, England.
-----Original Message-----
From: hariharan [mailto:hariharan@xxxxxxxxxxx]
Sent: 14 February 2003 04:52:AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PECL termination technique?
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Hi,
This is regarding a PECL termination. I'm presently reviewing a hardware
design, in that the designer has used a PECL to TTL converter for a clock
Oscillator's PECL output connecting to a CPLD via a PECL to TTL translator.
Here the designer has used a termination ie PECL - PECL (Differential), say
he has used a 120 ohm RES connecting the positive and negative of the
differnential pair.
(POS) +------33 ohms---------------------------+ (POS)
>
120 ohms
>
(NEG) - ------33 ohms---------------------------- - (Neg)
the devices are CY7B951-SC (Cypress) to Motorolla's (MC100ELT23D).
Here in the above case I understand the designer has opted for a power
consumption less termination. But the usual termination we go in for is
a Y termiantion ( with ref. to ONSEMI PECL design - Application note).
Can anyone help me out to understand how the designer would have arrived at
those values and the termination technique.
regards
Hariharan
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<DIV><SPAN class=3D328163704-14022003>Hi,</SPAN></DIV>
<DIV><SPAN class=3D328163704-14022003></SPAN> </DIV>
<DIV><SPAN class=3D328163704-14022003></SPAN><SPAN =
class=3D328163704-14022003>This=20
is regarding a PECL termination. I'm presently reviewing a hardware =
design, in=20
that the designer has used a PECL to TTL converter for a clock =
Oscillator's PECL=20
output connecting to a CPLD via a PECL to TTL translator. </SPAN></DIV>
<DIV><SPAN class=3D328163704-14022003></SPAN><SPAN =
class=3D328163704-14022003>Here=20
the designer has used a termination ie PECL - PECL (Differential), say =
he has=20
used a 120 ohm RES connecting the positive and negative of the =
differnential=20
pair.</SPAN></DIV>
<DIV><SPAN class=3D328163704-14022003></SPAN> </DIV>
<DIV><SPAN class=3D328163704-14022003></SPAN><SPAN=20
class=3D328163704-14022003> &nbs=
p; (POS)=20
+------33 ohms---------------------------+ (POS)</SPAN></DIV>
<DIV><SPAN=20
class=3D328163704-14022003> &nbs=
p;  =
; =
&=
nbsp; >=20
</SPAN></DIV>
<DIV><SPAN=20
class=3D328163704-14022003> &nbs=
p;  =
; =
&=
nbsp; 120=20
ohms</SPAN></DIV>
<DIV><SPAN=20
class=3D328163704-14022003> &nbs=
p;  =
; =
&=
nbsp; =20
></SPAN></DIV>
<DIV><SPAN=20
class=3D328163704-14022003> &nbs=
p; (NEG) =20
- ------33 ohms---------------------------- - (Neg)</SPAN></DIV>
<DIV><SPAN class=3D328163704-14022003></SPAN> </DIV>
<DIV><SPAN class=3D328163704-14022003>the devices are CY7B951-SC=20
(Cypress) to Motorolla's (MC100ELT23D). </SPAN></DIV>
<DIV><SPAN class=3D328163704-14022003></SPAN> </DIV>
<DIV><SPAN class=3D328163704-14022003>Here in the above case I =
understand the=20
designer has opted for a power consumption less termination. But the =
usual=20
termination we go in for is </SPAN></DIV>
<DIV><SPAN class=3D328163704-14022003>a Y termiantion ( with ref. to =
ONSEMI PECL=20
design - Application note).</SPAN></DIV>
<DIV><SPAN=20
class=3D328163704-14022003> &nbs=
p; =20
</SPAN></DIV>
<DIV> </DIV>
<DIV><SPAN class=3D328163704-14022003>Can anyone help me out to =
understand how the=20
designer would have arrived at those values and the termination=20
technique.</SPAN></DIV>
<DIV><SPAN class=3D328163704-14022003></SPAN> </DIV>
<DIV><SPAN class=3D328163704-14022003>regards</SPAN></DIV>
<DIV><SPAN class=3D328163704-14022003>Hariharan</SPAN></DIV>
<DIV><SPAN class=3D328163704-14022003></SPAN> </DIV>
<DIV><SPAN=20
class=3D328163704-14022003> &nbs=
p;  =
; =
=20
</SPAN></DIV>
<DIV><SPAN class=3D328163704-14022003></SPAN><BR> </DIV>
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