Hello PCIe Experts,
maybe somebody can answer one= questions for PCIe Gen3 clock compliance
especially with SSC.
F= or Gen3 clocking the spec defines different behavior of RX PLL/CDR,
depende= nt on "Data clocked" or "Common Clocked" RX
architecture.
The spec just recommends  with all unique combinations of ba= ndwidth
and peaking.
But some of them just seem not to be able t= o follow SSC for Data clocked
RXarchitecture reasonably. For several diffe= rent platforms I have seen
fails for this parameter when SSC is enabled. Ba= sed on these tests I do
notthink this is a question of SSC implementation = of the Cock source. Even
for some complete different platforms I do see a s= imilar risidual of SSC
after applying all filters/transfer functions.
=3D=3D> did somebody else observe something similar ? (and if yes = ..
what is your conclusion out of this fail? )
For data clocked i= t is necessary to compute the worst case T-Refclk-rms-DC
for all unique com= binations of peaking/BW. With this requirement i guess
all systems that I h= ave seen in the last time woudl fail.
For common clocked t is ju= st recommended to test all combinations of
peaking/BW to characterize = T-Refclk-RMS-CC jitter ... But seems not
required .. so is it allowed to se= lect the settings that pass the Test ?
(but common clocked is anyhow not fa= iling)
thanks and regards
Hermann=
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