[SI-LIST] Re: PCIX A/D WIDTH Min

  • From: Scott McMorrow <scott@xxxxxxxxxxxxx>
  • To: brahim@xxxxxxxxxxxx
  • Date: Thu, 06 Jun 2002 09:52:46 -0700

Brahim,

When you perform these simulations, make sure that you have a good model 
of the PCI-X device packages which include signal-to-signal coupling and 
power/ground modeling.  You will find that most of the noise on a PCI-X 
bus is developed in the package before the signals reach the PCB, and 
due to the low impedance drivers that reflected reverse crosstalk often 
saturates within the package.

As for the minimum trace width, that is dependent upon your board 
manufacturer, stackup and trace impedance. Typically most PCI-X boards 
are manufactured with 5 mil trace widths.

Regards,

scott


-- 
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com




Brahim Koudssi wrote:

>Dear SI list,
>
>
> I am designing a PCIX board and I would like to simulate the bus using
>Hspice to determine
> the minimum and maximum trace length of Address/Data, A/D lines.
>
> My question is the following:
>
> If I am to represent A/D as a pulse signal, what's the minimum  A/D
>Twidth I should use?
>
>Assume  Tclk=7.5ns
>
>Thanks,
>Brahim
>
>
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