[SI-LIST] Re: PCI-Express System Level Trace Impedance Value
- From: "Coleman, Dave" <dave.coleman@xxxxxxxxx>
- To: <tony_dunbar@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 16 Jul 2003 11:58:02 -0700
If I were specifying the board impedance target and tolerance, I think =
it would be preferable to tighten the tolerance around a lower or higher =
impedance target if possible, instead of having a more liberal tolerance =
around the 100 Ohms. An impedance target of 95 Ohms +/- 15% (assuming =
no cost adder) would be preferable to 100 Ohms +/- 20% since the tighter =
tolerance should result in lower jitter and (potentially) return loss. =
With a higher tolerance comes allowance for more mismatch (and thus more =
timing/voltage margin impact).
-dave
-----Original Message-----
From: Dunbar, Tony [mailto:tony_dunbar@xxxxxxxxxxx]
Sent: Wednesday, July 16, 2003 10:49 AM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Re: PCI-Express System Level Trace Impedance Value
Michael,
Layout guidelines for PCI Express published by Intel say 100ohms +/- 15% =
or
better "is desired". Other publications and papers are even more liberal =
and
suggest +/- 20%.
Regards,
Tony
-----Original Message-----
From: Chan, Michael (Eng Hou) [mailto:michael.chan@xxxxxx]
Sent: Tuesday, July 15, 2003 4:15 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PCI-Express System Level Trace Impedance Value
Hi:
I am looking for the board level differential impedance of the trace =
for
a PCI_EXPRESS bus. I know the connector has a differential impedance =
value
of 100 ohms. Is the system level ( board ) also has a 100 ohms =
difference
impedance value or something else? Thanks.
=20
=20
Regards,
Michael Chan
H-P Corp.
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