[SI-LIST] Re: PCI input setup time question
- From: "Jon Powell" <jonpowell@xxxxxxxxxxxx>
- To: <marko.pulli@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 24 Jun 2003 09:24:46 -0700
On most technologies you would generate a MIN and MAX data arrival time that
is used for doing total MIN MAX timing through a data path. The MIN and MAX
data arrival is usually done as:
MIN: (on rising) - time of data first crossing low Vin threshold
MAX: (on rising) - time of data LAST crossing of high Vin threshold (where
LAST takes into account any oscillation across threshold).
And the reverse for falling.
If you are doing through path timing, I would think this argument would be
true for PCI as well as any other technology. Most SI simulators will
generate this MIN MAX data arrival time for you and put it in a format
suitable for import to a timing verification engine. (SDD format?)
jon
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of marko.pulli@xxxxxxxxx
Sent: Tuesday, June 24, 2003 9:15 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PCI input setup time question
Hi all,
What is the correct voltage level for bussed signals when measuring =
input setup time in a PCI bus?
I have used either 0.5Vcc or 0.3Vcc (rising/falling) to be sure that the =
data is valid.
There is also 0.4Vcc (V_test) in the spec 4.2.3.3 Measurement and Test =
Conditions but the data isn't valid at that voltage level yet :-)
-Marko
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