[SI-LIST] Re: Newbie board question
- From: steve weir <weirsp@xxxxxxxxxx>
- To: glennj+@xxxxxxxxxx, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 14 May 2004 04:43:35 -0700
At 12:53 AM 5/14/2004 -0400, Glenn Judd wrote:
>(As this is a newbie question; apologies to those not
>interested.)
>
>Hi All,
>
>I have a nearly complete beta design of a high
>speed board. I've tried to follow principles
>gleaned from this list and other sources,
>but since my background is in CS (no grumbling=20
>please :) ), I thought it would be prudent to=20
>run my design past any altruistic readers here=20
>just to see if there are any obvious high level=20
>issues that I should be concerned with.
>
>Goal
>
>FPGA (Virtex-II) based signal processing board=20
>w/ core clock running @ 200 MHz. Basic signal=20
>is 12 bits @ 200 Msps. This is for academic=20
>research, so I'm more worried about correctness=20
>and low number of spins than I am about optimizing=20
>component cost etc.
>
>I/O
>
>Input1: 12 bits LVDS @ 200 MHz
>Output1: 2x12 bits CMOS @ 100 MHz (interleaving gives=20
> basic signal)
>(these I/Os will eventually be an intra-board signal,=20
>inter-board in prototype)
> =20
>Input2: 6 bits LVDS @ 400 MHz (DDR of basic signal)
>Output2: 6 bits LVDS @ 400 MHz (DDR of basic signal)
>(these I/Os are running inter-board over LVDS/SCSI cable
>w/ VHDCI connectors)
Works fine in VII if you use a dedicated DCM in each direction for the I/O.
>Stackup
>
>Layer Type Separation (mils)
>1 LVDS
> 8
>2 GND
> 8
>3 VCC 1.5 (powers FPGA core)
> 4.5
>4 VCC 2.5 (powers LVDS)
> 8
>5 CMOS (flooded w/ GND where possible)
> 4.5
>6 VCC 3.3 (powers CMOS)
> 8
>7 GND
> 8
>8 LVDS
>
>outer copper 1 ounce, inner 0.5 ounce
Usually two routing layers are needed, one for E-W, and the other for
N-S The LVDS on outer 1 oz Cu is not going to be well controlled.
However, this board is going to generate considerable EMI from power plane
resonances excited by those single ended CMOS signals at 100MHz.
You might try:
1 1/2 oz plated to 1 oz Components / 3.3V decoupling caps / low edge rate
sigs if routes avail and needed / ground hatch rest
5 mils
2 Ground
5 mils
3 CMOS / LVDS east - west
12 mils
4 3.3V 1oz
5 mils
5 2.5V 1 oz
12 mils
6 CMOS / LVDS north south
5 mils
7 Ground
5 mils
8 1/2 oz plated to 1 oz 1.5V islands w/routed connects / 2.5V & 1.5V
decoupling caps, and remainder ground hatch
In this stack-up, the fast stuff is all stripline, dominantly coupled to
ground. Emissions and impedance control will be much better. Ground is
pushed closer to the surface, improving EMI.
Core voltages tend to have a lot less junk on them then I/O. Islands of
1.5V with local decoupling caps will avoid cavity resonance and maintain Cu
balance. CMOS and LVDS on the same layer, just space according to 1/( 1 +
D/H^2 ) to limit cross talk appropriately. For 40 dB, you need about 48
mils from any CMOS line to the nearest LVDS parallel line that is of
significant length.
You may also wish to rethink whether layers 4 and 5 cannot be absorbed into
layers 1 / 8. How much DC current do you really have on those 2.5V and
3.3V supplies that you need whole planes? Ground is what you want to use
to return your AC currents.
Steve
>Decoupling Caps
>I have over 1 cap/power pin since I'm
>trying to err on the side of caution.
A starting point is a target impedance at some reasonable cut-off in the
50-100MHz region. Then knowing the thickness of your board, and the types
of capacitors you are willing to use, we can estimate the number of vias
needed. If minimum vias are your goal, we can use X2Y, or ordinary 0603 /
0402 caps. If minimum caps is your goal, we can use X2Y's, IDC's, or
alternatively 0603/0402's with multiple vias / pad.
>(Not showing caps near/required by voltage=20
>regulators)
Skip the multiple values. 1uF costs the same as 100nF in 0603. So, I
would just settle on 1uF caps in place of the 2.2nF, 22nF, and 100nF
caps. The larger capacitance of the 1uF capacitor reduces the likelihood
of anti resonance with the 4.7uF caps. If you are in 0402s just go for
100nF caps that are readily available.
Design the bulk capacitors as needed for your application. That means
understanding the power regulator and what impedance you are trying to hit.
Your options w/ the FPGA depend on the pin pitch. Sometimes you can marry
0402 caps to the power ground through holes.
>VCC
>1.5 2.5 3.3 Capacitor (uf)
>------------------------------
> 4* 10* 4* 0.0022=09
> 4* 6 6 0.022
> 2 6 2 0.1
> 2 2 2 1
> 1 1 1 4.7
> 1 1 1 47
>* =3D located under FPGA in middle of ball grid
>
>I'm using blind vias on the FPGA's center ground pins
>to create room underneath. This requires blind
>vias in two directions though (top for FPGA GND,=20
>bottom caps fanout). Naturally if I could get by=20
>with no-blind vias and only a couple caps directly=20
>under, that would be great. Since I really don't
>know if that's OK or not, I'm erring on the side of=20
>caution; I'd rather have a more expensive initial=20
>spin than a respin/power plane debug.
We can actually work these things out with additional information. What
kind of caps you are willing to use, and the via patterns will strongly
affect what is needed.
>Traces
>
>Used National's app notes for LVDS to determine differential
>pair spacing etc. LVDS trace sep is 5 mils. I'm using guard
>traces for all high speed signals (not sure if necessary...).
Don't use guard traces, just apply the separation that you would have had
with the guards. Guard traces unless via'd frequently make
resonators. Bad things can happen.
>Banking
>
>I've split the interleaved 12-bit 100 MHz CMOS signals
>across two IO banks each so that each bank always has
>6 (potential) changing IOs. I'm hoping to reduce
>simultaneous switching IOs and ground bounce issues here.
12, 100MHz signals are a non issue if you are source synchronously
timing. Timing from a common board clock but w/o using a DCM w/ LVCMOS or
LVTTL I/O standards could be difficult at 100MHz even with a -6 part. The
issues are going to be hold time coming into the part and set-up time
leaving it. This depends on what the timing looks like for what these
signals are talking to, and your DCM allocation.
>Design Success Criteria
>
>core clock speed
>200 MHz =3D ideal
>150 MHz =3D near ideal
>100 MHz =3D fair
>50 MHz =3D semi-functional
>< =3D expensive toy
Your core clock speed is getting up there for a VII FPGA. Whether you can
meet it or not depends on your logic and the size and speed grade of the
part. If 200MHz is important to you, I would get some help in reviewing
your design strategy and floorplan before you commit the PCB. ( Yes I sell
such services. However, I am on the West Coast. There s/b a number of
competent people in your area who can help you. If not, I am always happy
to scare up new business but edu usually means broke. )
>Again, I'm looking for high-level comments (even
>"you'll never succeed" would be OK :) ) and not
>expecting a detailed critique.
>
>Thanks in advance!
>
>Glenn
>
>
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