[SI-LIST] New Webcast on addressing the challenges at 10Gbps serial links

From: Salman Jiva <sjiva@xxxxxxxxxx>
To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Date: Mon, 8 Feb 2010 14:37:27 -0800

New Webcast on addressing the challenges at 10Gbps serial links
http://www.accelacomm.com/jaw/siemail/0/50783818/
Available Now, On-Demand
Length:  25 minutes

As serial data rates increase beyond 10 Gbps to address high-bandwidth 
applications (e.g., 40G/100G systems), board design challenges grow as well. 
Ensuring statistical reliability of a serializer/deserializer (SerDes) channel 
requires careful board design, as well as advanced silicon capabilities to 
handle losses due to PCB material properties and reflections due to 
discontinuities in the channel. In this webcast, we will discuss some of the 
solutions available to address these challenges and ensure high reliability for 
serial links at data rates beyond 10 Gbps.

In this 25-minute webcast, you'll learn how to:

 *   Address system challenges at high data rates
 *   Incorporate advanced FPGA silicon solutions to increase system reliability
 *   Increase productivity with advanced PCB tools and models
http://www.accelacomm.com/jaw/siemail/0/50783818/

Salman Jiva
408.544.6527
Altera Corporation
Product Marketing Manager
High End FPGAs



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[SI-LIST] New Webcast on addressing the challenges at 10Gbps serial links

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