[SI-LIST] New Positions Available

From: "Tomas Diaz (tdiaz)" <tdiaz@xxxxxxxxx>
To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Date: Sun, 4 Nov 2012 19:57:53 +0000
Hello,
My name is Tomas Diaz, and I'm the Recruiter for the Data Center Group within 
Cisco. We are current seeking to fill the following position(s), please apply 
in confidence to my email tdiaz@xxxxxxxxx<mailto:tdiaz@xxxxxxxxx>.

Thank you,

Tomas

Job Title: Signal Integrity Engineer, Technical Leader
Location: San Jose, CA

Opportunity Snapshot

In this role, you will have the opportunity to work in the hardware engineering 
team of SAVBU - Cisco's latest acquisition in the Data Center space. We are 
looking for candidates who strive in a fast paced start-up like environment. 
You will be part of a dedicated team, open communications, empowerment, 
innovation, teamwork and customer success are the foundations of the team. 
Thus, you set your own limits for learning and achievements.
We are looking for a motivated Senior Signal Integrity Engineer to contribute 
to the development of our next generation product.

http://www.cisco.com/en/US/products/ps10265/index.html

Job Requirements:

- 10+ years of experience in signal integrity with MSEE, Ph. D. Preferred
- Having deep knowledge of signal integrity theories, with proven track record 
in product delivery
- Not be afraid to take risks, and think out of the box
- Expert in simulation tools such as ADS, Hspice, SpectraQuest, and CST
- Hands on person who can do both simulations and lab measurements to validate 
the simulation results
- Has done validation of simulations results using TDR, Network Analyzer, 
Oscilloscopes and other lab equipment
- Familiar with multi gigabit serial busses, including PCIe, XAUI, KR, XFI, and 
SFI
- Contribute to the signaling and interconnect technology selection
- Definition and simulation of high speed interconnects using simulation tools
- Assess timing, noise margin, crosstalk, signal loss and signal integrity of 
all clocks and critical data signaling and develop noise and timing budgets.
- Familiar with package and board co-design methodology
- Has done Package and system level power integrity design methodology
- Backplane design experience and analog circuit knowledge are preferred
- Familiarity with high speed I/O's such as HSTL, SSTL, LVDS, LVPECL, and 
serial busses
- Familiar with Memory technologies such as DDR is preferred
- Ability of working effectively with other disciplines a must
- Excellent documentation, communication skills,
- Effective interaction with other engineering discipline skills a must


Job Title: Signal Integrity Engineer
Location: San Jose, CA

Opportunity Snapshot

In this role, you will have the opportunity to work in the hardware engineering 
team of SAVBU - Cisco's latest acquisition in the Data Center space. We are 
looking for candidates who strive in a fast paced start-up like environment. 
You will be part of a dedicated team, open communications, empowerment, 
innovation, teamwork and customer success are the foundations of the team. 
Thus, you set your own limits for learning and achievements.
We are looking for a motivated Signal Integrity Engineer to contribute to the 
development of our next generation product.

http://www.cisco.com/en/US/products/ps10265/index.html

Job Requirements:

- 1 + years of experience in signal integrity
- Familiar with simulation tools such as ADS, Hspice, SpectraQuest, and CST
- Hands on person who can do both simulations and lab measurements to validate 
the simulation results
- Has done validation of simulations results using TDR, Network Analyzer, 
Oscilloscopes and other lab equipment
- Familiar with multi gigabit serial busses, including PCIe, XAUI, KR, XFI, and 
SFI
- Contribute to the signaling and interconnect technology selection
- Definition and simulation of high speed interconnects using simulation tools
- Assess timing, noise margin, crosstalk, signal loss and signal
integrity of all clocks and critical data signaling and develop noise and 
timing budgets.
- Familiar with package and board co-design methodology
- Has done Package and system level power integrity design methodology
- Backplane design experience and analog circuit knowledge are preferred
- Familiarity with high speed I/O's such as HSTL, SSTL, LVDS, LVPECL, and 
serial busses
- Familiar with Memory technologies such as DDR is preferred
- Ability of working effectively with other disciplines a must
- Excellent documentation, communication skills,
- Effective interaction with other engineering discipline skills a must
- Minimum of 1+ years of relative experience with MSEE, PHD preferred.



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[SI-LIST] New Positions Available

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