[SI-LIST] Multi-board simulation for SODIMM analysis
- From: Mohamed Khaleel <gotokhaleel@xxxxxxxxx>
- To: si-list <si-list@xxxxxxxxxxxxx>
- Date: Sun, 15 Jan 2012 19:33:25 +0530
Hello,
I am doing a multi board simulation to check the signal quality at the DDR3
ICs of SODIMM. We have two SODIMM modules connected to the processor. I am
using the Micron EBD model for the SODIMMs. I extracted an address signal
and I have the following 3 doubts.
The extracted topology is available in the following link.
http://dl.dropbox.com/u/7573090/SODIMM_Topology.pdf
or
https://dl.dropbox.com/u/7573090/SODIMM_Topology.pdf
1. From the above topology, I could see that the Resistor network comes
first then followed by the individual DDR3 IC buffers. I thought the
Resistor network should be placed at the end. Please correct if I am
missing something.
2. The RN is assigned an IBIS model in the EBD model. Is this the way
Micron does the parallel termination model? Can I assume that resistor and
the VTT are taken into the IBIS model itself?
3. The board edge connector of SODIMM is called EBD_CN. Do we need to
assign a model for this? Or it is taken into consideration in the EBD model
itself?
Any help/suggestion will be helpful. Thanks.
Regards,
Khaleel
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