[SI-LIST] Re: Multiboard Analysis
- From: "Erfan" <erfan@xxxxxxxxxx>
- To: "'narasimha rao'" <narasimharaopatil@xxxxxxxxx>
- Date: Thu, 1 Jul 2010 14:12:09 +0530
Hello Narasimha,
You can find the DIMM module datasheet, in that he will clearly mention how
the clk is being routed to the Chips (topology).
It won't be separate clock for all the chips as it is not required. Clocks
will be shared across 2 chips or mostly 4.
And you have mentioned that there are 5 chips, please cross check this once.
It will be even multiples always.
Regards,
Erfan
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of narasimha rao
Sent: Thursday, July 01, 2010 1:44 PM
To: steve weir
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Multiboard Analysis
Thanks for the reply,
But for the diff clk it is not been defined, truly speaking DIMM module has
got 5-chips inside and each will have separate clk.
Regards,
Narasimha
--- On Thu, 7/1/10, steve weir <weirsi@xxxxxxxxxx> wrote:
From: steve weir <weirsi@xxxxxxxxxx>
Subject: [SI-LIST] Re: Multiboard Analysis
To: "narasimha rao" <narasimharaopatil@xxxxxxxxx>
Cc: si-list@xxxxxxxxxxxxx
Date: Thursday, July 1, 2010, 11:06 AM
DIMM specs are available from JEDEC.
Steve.
narasimha rao wrote:
> Hi All,
> In one processor interfaced with DDR2 MODULE analysis, I'm facing a
problem in getting topology for ddr2 clk(diff).
>
> Can anybody help me in solving this?
>
> Regards,
> Narasimha
>
>
>
>
>
>
>
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