[SI-LIST] Lowest cost way to implement 16 5Gbps SERDES channels
- From: Chris Johnson <cjohnson@xxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 04 Aug 2009 09:54:53 -0400
I've been looking at ways to implement 16 5Gbps SERDES channels and it
seems that to get this speed you need to use one of the really expensive
FPGAs (i.e. much greater than $1K per chip). I don't need a ton of
non-SERDES logic, so I'm looking for a more reasonably priced solution.
I'm even amenable to non-FPGA implementations. Any thoughts?
Thanks,
Chris
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