Folks: I have a need for in-depth information regarding buildable footprints for Inter-digitated bypass capacitors (IDCs) in the 0805 size. I am reluctant to recommend multiple via hits in the pad since I have questions whether it is worth the hassle. I also need to find out what is any inductance inductance effects can be expected when there are thermal vias at the connection points in the power/ground planes rather than a standard via. An equivalent circuit would be helpful with different element values for different pad/via configurations questioned above. Thanks - ed sayre +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ | NORTH EAST SYSTEMS ASSOCIATES, INC. | | ------------------------------------- | | "High Performance Engineering & Design" | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ | Dr. Ed Sayre e-mail: esayre@xxxxxxxx | | NESA, Inc. http://www.nesa.com/ | | Primrose Park Tel +1.978.392-8787 | | 5 LAN Drive, Ste 200 Fax +1.978.392-8686 | | Westford, MA 01886 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu