[SI-LIST] Low ESL capacitor footprints

  • From: "Dr. Edward P. Sayre" <esayre@xxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Thu, 09 Sep 2004 10:06:37 -0400

Folks:

I have a need for in-depth information regarding buildable footprints for 
Inter-digitated bypass capacitors (IDCs) in the 0805 size.  I am reluctant 
to recommend multiple via hits in the pad since I have questions whether it 
is worth the hassle.

I also need to find out what is any inductance inductance effects can be 
expected when there are thermal vias at the connection points in the 
power/ground planes rather than a standard via.

An equivalent circuit would be helpful with different element values for 
different pad/via configurations questioned above.

Thanks -

ed sayre




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