[SI-LIST] Re: Load calculation and Buffer.
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Nirmale G <nirmale@xxxxxxxxxxxxxxx>
- Date: Sat, 25 Oct 2008 22:08:25 -0700
8mA is the nominal output. Look at the IBIS model for the expected V/I
curve. You will likely find the drive strength is much higher at the
start of the rise / fall. However, 8mA is still very weak for 3.3V
swing at 200MHz+. A 3.3V CMOS buffer such as you have selected is a
poor choice for signaling much above 100MHz. If you must signal with
3.3V then at least increase the drive strength of your buffer.
If you are just trying to characterize your ICs and/or interconnect and
have to use that weak 3.3V driver, lower the signaling rate.
Steve.
Nirmale G wrote:
> Hi ,
>
>
> I have 20 i/o lines from a test board to be interfaced to FPGA for
> analysis. The test board chip pad can max drive a current of 8mA , max
> frequency is 216MHz , and logic level is 3.3V.
>
>
>
> Calculation for load, C = I * dt/ dv
>
>
>
> C = 8e-3 * rise time / 3.3
>
>
>
> Taking Rise time as (0.46ns)10% of period (4.6 ns) gives the C = 1.12pF ,
> which is very less .
>
> But, For any buffer/ line driver the typical input capacitance is 5 to 7pf
> .
>
>
>
> Any thoughts on the interface and my calculations for load.
>
>
>
>
>
> Regards
>
> Nirmale G
>
>
>
>
>
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