[SI-LIST] LVDS reciever hysteresis according to IEEE and TIA-EIA

From: Peter Sørensen <pso@xxxxxxxxxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Date: Fri, 01 Aug 2008 13:41:39 +0200

Hi everyone
We use  LVDS receivers as zero crossing (Added DC offset) comparators.
The reason for this is that normal analog comparators are too slow for 
270 Mbps.

I have found that some LVDS receivers has a hysteresis while some do not.
We need some without hysteresis,  one with CMOS output and one with LVDS 
output.
DS90LV001 (LVDS in and out) has about 50 mV hysteresis, while FIN1001 
(LVDS in, CMOS out) does not.
I am waiting for FIN1101 to see if that can replace the DS90LV001.

(A smaller hysteresis of max 10mV or a time limited  hysteresis would be 
fine to avoid false spikes, as long as the threshold is back to zero at 
the next real edge.
I believe a time limited hysteresis can be made by an AC coupled 
feedback when the bitrate is fixed, but i demands a IC without build in 
DC hysteresis).

TI seems to specify the hysteresis while National does not, Fairchild 
seems to have skipped the hysteresis and thereby maybe the IEEE spec.

I found and old SI-list question without an answer I quote:
"In receiver electrical specifications of IEEE standard for LVDS we have 
a minimum value for hysteresis(25 mV) where as there is no such 
specification for LVDS receiver in TIA-EIA standard. My question is why 
is it so, I mean what is the reason behind this difference in 
specifications? Any comment is welcome.
Regards Rajesh Kaushik"

I do not have access to these standards so I only have above statement 
to work from, can anyone confirm?

The National data sheet only states: Compatible ANSI/TIA/EIA-644-A LVDS 
standard
There is no reference to IEEE:

best regards

Peter Sørensen
Protelevision





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[SI-LIST] LVDS reciever hysteresis according to IEEE and TIA-EIA

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