[SI-LIST] LVDS Interface Question

From: <medve.laszlo@xxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Date: Tue, 8 Dec 2009 9:52:42 +0100
Hi all,

I'm working on a design which use a Virtex-6 as an LVDS transmitter and an 
Analog Devices DAC as a receiver. The problem with it, that the FPGA buffer 
based on ANSI/TIA/EIA-644-A Standard and the receicer based on IEEE-1596.3-1996 
(SCI-LVDS) Reduced Range Link Standard. It cause differences in Electrical 
Parameters:
FPGA:
  Output Voltage Range: 825mV...1675mV
DAC:
  Input Voltage Range: 825mV...1575mV

Our signalling rate is 135MHz. I made some IBIS simulations and it shows that 
the input voltage doesn't exceed the maximum, but very close to this ~1570mV. 
Another problem is that I haven't got these standards, and I didn't find any 
overshoot specification (area, peak) on receiver side. I see 2 possibilities to 
guarantee long time reliablity:
1) Reducing input voltage with external circuit. Do you know any good solution 
for it?
2) If overshoot specification gives enough reserve, it can be compatible.... 
Could somebody give information from IEEE 1596.3 Standard?

Is there anybody who met with this question before? How did you solve this?

Thanks for all the help!

Best Regards,
Laszlo
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[SI-LIST] LVDS Interface Question

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