[SI-LIST] LPDRR3 spec questions

From: Hari Anand Ravi <r.harianand@xxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Date: Mon, 27 Aug 2012 15:18:27 +0530

Hi Experts,
I have a few questions on LPDDR3 JEDEC spec (Please refer to the attached
doc)


Pg 100: Table 8.7.4 RZQ I-V Curve:

I find I-V curves only for the un-calibrated case (whereas in LPDDR2 JEDEC
spec we have I-V curves for both calibrated and ZQ-Reset case) . So for
LPDDR3 , would it suffice to meet the impedance of 240+/-15% only at
0.5VDDQ for the calibrated case ?



Pg 102 : Section 8.7.5

For ODT , only Parallel termination is supported ?  (I mean ,only Pull-up
and no Thevenin termination)



Pg 116 : Section 11.5 (Table  63)

Are the AC System timings specified correspond to the calibrated
driver?(timings like tCK(avg) , Duty cycle Jitter)


Thanks,

Hari



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[SI-LIST] LPDRR3 spec questions

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