Quick note, and boy does it feel weird for me to defend The Man, but:
Back when I worked for Agilent (a.k.a., Keysight), I never held back and two
out of the three bosses I had during my tenure there defended my right to
question executives and management. One even quoted "Dave and Bill" in my
defense. I once told an SVP that I felt like Huck Finn with a hand on a
wooden tiller trying to turn a container ship and he actually got it and let
me turn the ship (jitter).
Of course, there was also the time I declared that as long as the concerns
of engineers were ignored, I would never attend another company meeting.
That went over less well.
;)
_____________________________
Ransom W. Stephens, Ph.D.
Signal Integrity Sage
Named the 2017 Jim Williams ACE Contributor of the Year for content that
advances engineering and design
Ransom's Notes: Training, content, and consulting/analysis since 2005
www.ransomsnotes.com
Measure of Things - Science & Technology blog at Electronics Design News:
science from the perspective of a technologist, technology from the
perspective of a scientist
Eye on the Standards - Keeping you up to date on developments in high speed
specifications
Twitting @ransomstephens
LinkedIn, Facebook and all that stuff
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Scott McMorrow
Sent: Wednesday, October 04, 2017 3:30 PM
To: chris.cheng@xxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Keynote Speeches from EDICon Last month
Chris understands. Sometimes in betting your job you just have to move
ahead to another opportunity before the current one overtakes you.
Rambus was a great technology for streams that could be pipelined. It was
totally inappropriate for Servers or Laptops, and was marginal even in
Desktops at the time. Follow on chipsets using SDRAM were also hampered
by the bus. IIRC Intel took around a $1B loss in chipsets around this
time, not to mention several processors in the family that were aborted
before making it to market.
The nice thing about being a consultant who had many clients was that I
was not beholden to Intel or any company, so I could tell the truth in
meetings. Perhaps, I would argue, if you are stifling yourself in
meetings and communication, because of culture, pushback from above, or
the fear of being fired, you might be in the wrong job.
Obviously these are often personal decisions that one must make, but from
where I'm sitting I want engineers to challenge me, to call BS, and to
speak the convictions of their own engineering and personal knowledge.
Always.
Scott McMorrow, CTO Signal Integrity Group
Samtec
Office 401-284-1827 | +1-800-726-8329
www.samtec.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Cheng, Chris
Sent: Wednesday, October 4, 2017 5:37 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Keynote Speeches from EDICon Last month
There are plenty of Nintando64 and PlayStation with RAMBUS to answer your
how practical it is question.
When Bill Gunning and I was working on the first GTL systems, the target
impedance was in the 30's. All the server backplanes I designed for that
workstation company was in that range during that time. Bill was just
borrowing some of his old tricks in designing ECL bus with lower impedance
to minimize heavy loading impact on propagation delay and impedance
mismatch.
Again, I am not here to defend RAMBUS's patent troll practice or lack of
attention to memory latency. But to say the electrical design is
fundamentally flawed does not give justice to many things that came after
it. ALL the AGTL FSB from Intel, DDR1,2,3,4 are double date rate source
synchronous buses.
And even for that memory latency issue has a solution. We had a server
design almost the same as RAMBUS architecture before RAMBUS even exist.
You just have to double your memory and FSB bus width. That's why I had to
pull my hair out to design those crazy 1000+ pins processor packages in
that company. And you see those papers from some members of Si-list
describing how much struggle they had to deal with Swiss cheesed power
planes power delivery and signals routing through anti-pad gaps. Is it
more practical to do that vs. pushing bandwidth per pin and dropping the
bus impedance ?
It's one thing when you are a workstation/server company that ships a few
thousands of processors a year with high margin. You can bury your package
and huge PCB cost for a wide bus in your profit margin.
It's another thing when you are King of processors and ship 100mil+ units
a year. At a few cents per pin per package, if you half your bus width, a
few $$ savings times a 100 million is a lot of money. More than enough to
justify even the performance degradation and engineering resources to make
that happen.
I served both masters and they asked me to do drastically different goals.
But I fully understand where they came from. SI exist to make a particular
system architecture works. That is very different from just making
everything as fast as possible with the coolest technology.
And to get back to Scott's original point. If you think something is not
good, do something about it. ServerWorks did and for a while they cornered
the Intel workstation/server chipset market. Before Intel can react to
correct itself, they exited with an 1 billion M&A with Broadcom. Now
that's a cool Unicorn story.
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Enterprise Company
+1 510 344 4439/ Tel
chris.cheng@xxxxxxx / Email
4209 Technology Dr
Fremont, CA 94538
USA
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Lee Ritchey
Sent: Wednesday, October 04, 2017 10:34 AM
To: dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Keynote Speeches from EDICon Last month
During the 80s, I ran a design company that was designing PCBs for a group
of engineers at Lawrence Livermore Labs for a super computer for the US
Navy. The team that eventually formed Rambus was on that project and
wanted us to design a transmission line whose impedance was 28 ohms, not
impossible, but not very practical.
The navy cancelled the project and that team went on to form Rambus.
We wondered at the time how practical the idea was. Time showed us.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of heyfitch (Redacted sender "heyfitch" for DMARC)
Sent: Tuesday, October 3, 2017 2:34 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Keynote Speeches from EDICon Last month
Sent from my phone
On Oct 3, 2017, at 13:47, Lyndell Asbenson <Lyndell.Asbenson@xxxxxxxxxxx>
wrote:
Chris,
Regarding RAMBUS, it too had a lot of daemons. I have a wonderful plaque
celebrating our achievement in the Intel Chipset 820, and 840. The 840
was the 1st Intel Workstation utilizing high speed RAMBUS memory. What we
were attempting to do is figure out how to test the chipsets with RAMBUS
interface in very high volume manufacturing. This brought us fact to face
with all kinds of SI challenges we had never before seen. And had a very
short time to figure out. We know we had to test it at speed, yet there
was no production tester fast enough to do the job. This required a new
technology in testing call flyby channel multiplexing.
Regards,
Lyndell Lee Asbenson
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Cheng, Chris
Sent: Monday, October 2, 2017 11:07 PM
To: si-list@freelists.
Subject: [SI-LIST] Re: Keynote Speeches from EDICon Last month
Funny you mention Merced while Scott was talking about RAMBUS. 460GX
chipset was using PC100 SDRAM, not RAMBUS.
Merced had a lot of daemons, RAMBUS was not one of it.
And I sat through the decision process in the other processor company when
Bill Joy and Andy Bechtolsheim overrule the engineers recommendation to
use RAMBUS.
They correctly realized that bandwidth per pin could not justified the
degraded performance due to increase in memory latency imposed by RAMBUS.
Speed and signal integrity was never a concern and I know both the
engineer responsible to make that happen in RAMBUS and the engineer in
that workstation company tasked to make sure it worked.
RAMBUS exist to address a simple problem at that time, highest bandwidth
per pin for cost sensitive application. And it had plenty of examples in
Nintando64 and PlayStation. And Intel always had an alternative as backup,
it's called ServerWorks.
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Enterprise Company
+1 510 344 4439/ Tel
chris.cheng@xxxxxxx / Email
4209 Technology Dr
Fremont, CA 94538
USA
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of Lee Ritchey
Sent: Monday, October 02, 2017 11:40 AM
To: Scott@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Keynote Speeches from EDICon Last month
Scott,
Almost makes me want to go out and become an engineer! Nice work!
Didn't know you lived through the Intel Merced disaster! Only time I ever
heard a CEO admit publicly that Intel had made that mistake. Craig Barret
did that.
I watched the Apollo landing because I had a radio on board. That design
was my first job out of college. Couldn't believe they gave such
important
jobs to beginners! But, then, everyone on that project was a beginner at
designing those things!
Lee
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of Scott McMorrow
Sent: Monday, October 2, 2017 10:02 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Keynote Speeches from EDICon Last month
https://www.signalintegrityjournal.com/articles/567-edi-con-usa-keynote-
talk
s---bet-your-job-5g-in-5-years-and-tm-value
Scott McMorrow, CTO Signal Integrity Group Samtec Office 401-284-1827 |
+1-800-726-8329 www.samtec.com<http://www.samtec.com/>
This email and any appended documents are only for the intended
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