Xilinx Inc. in San Jose has an immediate job opening for a Staff Packaging
Engineer. Please see the following job description.
If interested in this position, please respond to
hong.shi@xxxxxxxxxx<mailto:hong.shi@xxxxxxxxxx> with your resume and/or
questions.
-Ray Anderson
Senior signal Integrity Staff Engineer
Xilinx Inc.
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Job Title: Staff Packaging Engineer
Detailed Description
The candidate will be responsible for driving package design integration,
verification and characterization in advanced FPGA systems, incorporating
silicon/TSV, package stack-up/routing/PDN, discrete decoupling capacitors and
system board interfaces. To utilize techniques in EM (Electromagnetic) and
Circuit model generation, simulation, and validation for correlating hardware
measurements versus pre/post-layout simulation, effecting a signal integrity
driven design flow for advanced FPGA product development. While working as a
member of a cross functional team, the candidate must optimize system level
performance in areas including Power integrity, High speed IO/SSO, and
Multi-Gigabit Transceivers. Drive cost reduction through adoption of leading
edge package technology while achieving performance driven objectives.
Job Requirements
BS in EECS and 5-7 years (MS in EECS with 3-5 year) direct experience in
package design is required. Demonstrated skills in designing large flipchip
BGA devices (>1900 pins) from product definition, die floor planning, package
architecture and die-package co-designs. Knowledge of high speed/RF designs,
circuit and package modeling, system level simulation, and physical layout
design. Familiarity with EM tools/platforms such as Ansoft HFSS,
Cadence/Sigrity PowerSI/Speed2000/XcitePI, HSPICE/ADS system simulator, Cadence
APD, Matlab/Python, and script language. This candidate is required to have
both expert-level electrical and design-level package layout skills.
Thorough understanding of S-parameter modeling methodology, Power Integrity
concepts and principles, Simulation/debugging insights, Physical
scaling/dimension implications to EM behavior of silicon circuits, transmission
paths/media, discrete/passive components, and integration of
silicon/package/capacitors/ printed circuit board structures. Package design
experience in high-speed IOs including multi-gigabit SerDes transceivers and
DDR memory IO interfaces. Clear understanding of power distribution network
design and optimization techniques. Cost conscious design principles and
experience.
]
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