[SI-LIST] Job Opening- Lead SI engineer
- From: "SunMan Engineering, Inc." <kopal@xxxxxxxxxxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 11 Nov 2003 12:15:19 -0800
Dear All,
There is an opening for a Lead SI engineer (Board level).
Please mail your response to: kopal@xxxxxxxxxxxxxxxxxxxxxx
JOB DESCRIPTION
SENIOR SIGNAL INTEGRITY ENGINEER
We are seeking a strong and versatile Senior Signal Integrity Engineer who
has excellent experience with board level simulation. He/She will be
involved with the board design and development effort through all phases
including analysis, design, layout, simulation, prototype bring-up, test,
complete design documentation, and release to manufacturing. He/ She is
expected to understand signal integrity issues, and board layout design
rules. Candidate should be a self-starter who thrives in fast-paced
environments and employs creative problem solving to overcome engineering
challenges.
QUALIFICATION REQUIREMENTS:
MSEE Plus 3+ years (or BSEE with 5+ years) of industry experience or (PhD
preferred)
The candidate must be an expert in the following:
*Prelayout signal integrity simulation including topology studies, routing
studies, IO buffer selection, Pkg. parasitics/delays effects, etc.. (Mentor
ISIS Preview-part of the Innoveda Package)
*Prelayout timing analysis (creating budgets per interface) including
common clock, ddr, and qdr interfaces (Hand calculations, and Mentor ISIS
Preview-part of the Innoveda Package)
*Power integrity/Noise margin analysis/calculations, decoupling schemes,
etc. (Sigrity)
*Defining placement requirements based on the above criteria
*Creating topologies, constraints, rules using Cadence's allegro and
SpecctraQuest)
*Postlayout SI and timing analysis (simulating secondary effects
(crosstalk, intersymbol interference, sso, jitter, etc. and their effects
on the overall budgets) to define timing violations.
*Expertise in Cadence Spectra-Quest and Mentor Graphic Hyperlynx or XTK.
*Expert in IBIS Modeling. (Preferable)
*Expert in HSPICE Model Extraction (Preferable)
*Familiar with DDR/QDR interfaces (chip-to-chip, SDRAM (DDR), SRAM (QDR).
*Simultaneous switching output analysis.
*Simulations of device I/O to reduce overshoot and undershoot (which can
cause increased noise on power planes due to return currents).
*Crosstalk analysis of signals to reduce noise.
*Return current analysis for noise reduction.
*Proper transmission line impedance control.
*Lab measurements using oscilloscopes, spectrum analyzers, etc. for
verification.
Thank you.
Regards,
Kopal Nema
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