I am looking for candidates to fill an internship in my group at Altera. Requirements for candidates include: 1. Basic knowledge of signal integrity characterization techniques. 2. Familiarity with high-speed lab instruments such as real-time scopes, equivalent-time scopes, spectrum analyzers, BERTs, etc. 3. Strong knowledge of analog electronic circuits such as PLL, CDR, and high speed I/O buffers. 4. Knowledge of VHDL, Verilog, and Labview/Labwindows/TestStand is a plus. The internship is for a duration of six (6) months, beginning as soon as possible. Please send resumes to me at dchow@xxxxxxxxxx Thanks! =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Daniel Chow, Ph.D. ALTERA Office: (408) 544-8100 Fax: (408) 544-7602 Email: dchow@xxxxxxxxxx =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu