[SI-LIST] Interconnect Simulations

From: manthos labropoulos <manthoslmp@xxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Date: Mon, 19 May 2003 17:42:30 +0100 (BST)


Dear all,

I am trying to simulate a SoC bus in order to observe
the crosstalk phenomena. For that reason i am modeling
the SoC interconnects with an RLC distributed model
(using FastCap and FastHenry).

In my final model in Hspice i am doing some
simulations with drivers with output resistance 50
Ohms and receivers with input capacitances 500fF. 

The input signals i am using have 1GHz frequency and
85ps rise/fall time.

Can you please tell me if the frequency and the
rise/fall times i am using are close to real life
examples ?
Do you think that these values are correct and can SoC
buses reach such frequencies (1GHz) and rise/fall
times (85ps) ?

If not then which do you think are the more suitable
values i should use ?

Thanks
Matheos  

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[SI-LIST] Interconnect Simulations

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