[SI-LIST] Re: Initial Delays in V-t Rise/Fall Curves in IBIS
- From: "Muranyi, Arpad" <Arpad_Muranyi@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 22 Oct 2010 07:03:19 -0700
Deepak,
You completely misunderstood Pugahz's question. He was talking about
the beginning of the V-t curves having a certain amount of horizontal
line before the transition (edge) begins. This is a very common
thing in IBIS models and this "dead time" represents a delay inside
the buffer.
Arpad
=======================================================================
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of deepak Engineer
Sent: Friday, October 22, 2010 8:50 AM
To: Pugazharasan Selvanathan - ERS, HCL Tech
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Initial Delays in V-t Rise/Fall Curves in IBIS
Hi P,
Usually you get a model with delay information for differential signals
only.
But never seen a model with intial delay..
your model looks like a more then IBIS model and less then Spice model..
you should follow the IBIS syntax and remove the unnecessary
informations.
are there any standard timing specification for DDR3 Controller?
>>
this depends upon the vendors..usually they provide a track lenght and
mismatch between different groups of signal..(it depends upon the
substrate
delay or chip internal delay).
As you are making you own controller, you need to find out an internal
delay
and then start a simulation...
based on best result you have to create a guideline to user...
this guideline will be based on internal delay plus condition to get a
best
performance and pcb track delay..
refer this pdf for more information or standard
http://www.hynix.com/inc/pdfDownload.jsp?path=/datasheet/Timing_Device/D
DR3_device_operation_timing_diagram.pdf
Best of luck,
Deepak
On 22 October 2010 15:32, Pugazharasan Selvanathan - ERS, HCL Tech <
pugazharasan.s@xxxxxxx> wrote:
> Hi all,
> Am doing timing analysis for DDR3 interface with Hyperlynx. I need to
> validate the DDR3 controller and DRAM IBIS models before using them in
> simulations. Both the models have some amount of initial time delays
in
> their V-t curves. I understand that this initial non-switching time
should
> be removed from the IBIS models before using them in timing analysis
for
> source synchronous interfaces like DDR3.
>
> Have a few questions now...
>
>
> 1. How much will be impact of this "removing initial delays" on
the
> setup and hold time margins?
>
> 2. If the initial non-switching delay be removed, why it should
be
> specified in the IBIS model first? Excluding the relative delay
between
> different V-t tables.
>
> 3. If the initial delays has to be removed, what should be the %
> Voltage Threshold I should use?
>
> Also, are there any standard timing specification for DDR3 Controller?
We
> are yet to receive that from the ASIC vendor, but wanted to go with
default
> timing spec. Right now we are in the process of delay matching the
> addr./Clock/DQ/DQS group. So this information will of much help.
>
> For strict timing analysis, should I have to include the package
delays
> also (Delay from die to pin) of DDR3 compliant DRAM in the timing
margin
> calculations?
>
> Regards,
> Pugazh
>
>
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