Hello,
I am running some simulations on Hyperlynx for a DDR3 memory and I just
noticed there is a drop-down menu for the probes location with the
following options:
- always at the pin
- always at the die
- Per each IC model's setting.
I never noticed this menu before although my experience with hyperlynx is
quite limited. I think I have always used the "always at the pin" option.
Does anyone have experience with this menu?
Has any have experience with the option "per each IC model's setting"?
I notice the option "always at the die" change significantly the result and
the result is worse. I assume this option takes into account the parameters
R_pkg, L_pkg and C_pkg defined on the IBIS model.Shown below
My approach would be to use only the "always at the pin" option as what I'm
simulating and designing is the interconnect at the pcb level. I'm not
entirely sure what can be done to account or mitigate the effect of the R,
L C package.
Could someone clarify when to use each of the options?
Kind regards,
Jesus
[Component] KINTEX7
[Manufacturer] Xilinx Inc.
[Package]
|FFG676
|variable typ min max
R_pkg 804.28m 202.98m 1461.33m
L_pkg 7.04nH 2.26nH 12.00nH
C_pkg 2.88pF 1.48pF 4.24pF
[Component] MT41J128M16JT
[Package Model] v89c_96ball_pkg
[Manufacturer] Micron Technology,Inc.
[Package]
| typ min max
R_pkg 345.04m 192.55m 567.10m
L_pkg 1.78nH 0.861nH 3.365nH
C_pkg 0.36pF 0.254pF 0.524pF
,
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