[SI-LIST] Re: How to simulate the signal going into connector
- From: Aneesh G <aneesh.govindan@xxxxxxxxx>
- To: Shahbaz Assad <shahbaz_assad@xxxxxxxxxxx>
- Date: Mon, 21 Jun 2010 17:10:52 +0530
Hi Shahbaz,
Usually for connectors we will not get the IBIS models. Therefore we
need to take the IDEAL RLC Values for the each connector pins and do the
analysis. You can assign RLC values for the connector on one side and ibis
models for DDR on other side and do the analysis.
--
Warm Regards
Aneesh G
On Mon, Jun 21, 2010 at 4:53 PM, Shahbaz Assad <shahbaz_assad@xxxxxxxxxxx>wrote:
> Hi Experts,
>
> I want to simulate some DDR2 signal that are going into the mating
> connector. The DDR2 is on the daughter card and it has to interface with the
> FPGA.
> Now please tell me how to simulate the DDR2 signals on the connector pins.
> I dont know what FPGA we are using on main board. I want to see my signal on
> the connector only.
>
> Tell me what is the best way to study the case?
>
> -shahbaz
>
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