I reviewed a design a couple of years ago. At first one out of the 5-6 boards
started to burn after a few hours of power. Then the 2nd, then the third. It
was root caused to be a 4 mil trace on the path of a few Amperes of current. It
was a design miss. The short net was not named in schematic and was not
assigned power property. I don't have evidence but I suspected that the trace
was heated, melted, continued to generate heat until the liquid copper had a
place to go, then stopped with an open.
Kent Zhang
Hardware Engineer, Intel
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Jeff Loyer
Sent: Wednesday, January 27, 2016 10:50 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: How to create a "fuse" in a PCB?
I apologize – it seems I wasn’t clear. I was being sarcastic with the term
“fuse” in the title. I don’t intentionally want to create a fuse in a PCB
design. I was wondering if folks had inadvertently created them (had designs
that burned either the dielectric material or their conductors).
Sorry for the confusion.
*Jeff Loyer*
Can anyone share their experience(s) with designs that have failed due to
excessive heat caused by excessive current in their PDN? I’ve been reading
IPC-2152 and Doug Brooks’ articles and wonder if you could create a power
delivery shape that would provide adequate voltage to the load(s) and yet heat
excessively. From what I’ve read, the thermal conductivity of copper and FR4
is such that, for any reasonable case, the heat generated would be dissipated
by adjacent copper and FR4. I suspect the active components would have much
more influence on the PCB temperature than the passive PDN shapes, but don’t
have any concrete information on that. Taken to its extreme, I wonder what
would happen if you had a 1-micron wide trace that was only 1-micron long, with
large planes on either side of that trace.
Its short length keeps it from being highly resistive, but the current density
is obviously very high in that 1-micron trace. While there may not be much
voltage drop, would the heat generated be dissipated by the adjacent large
copper shapes which have very low current density (generating very little heat)?
Right now I suspect that most shapes which provide adequate voltage to the
loads also provide adequate thermal dissipation. I can envision some scenarios
where this might not be true – an outer layer that’s been highly perforated by
BGA anti-pads, underneath a very hot part (or perhaps next to some very hot
parts), for instance. But, I’d like to hear from others who have had
experience in this area. How have you created a fuse (accidentally or on
purpose)? What methods have you used to mitigate excessive heat in your PDN,
apart from using minimum trace width constraints in IPC-2152?
I also welcome references to published works in this area.
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big plane | | big plane
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short, narrow trace
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Thanks in advance,
*Jeff Loyer*
Signal and Power Integrity Product Manager, Altium
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