[SI-LIST] Gigabit Channel Design Guidelines NetSeminar
- From: "Salman Jiva" <sjiva@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 9 Jul 2007 14:23:17 -0700
Netseminar by Leonard Dieguez on High-Speed serial channel design. This
is on-demand so you can view anytime.
http://www.altera.com/education/net_seminars/all/ns-gigabit-interconnect
.html
http://tinyurl.com/ypzsf3
(tiny URL version)
Leonard had sent this earlier, but it seems that it did not get sent to
many of the subscribers. Apologies to anyone who received this twice.
Overview:
Though high-speed serial links increase data throughput and reduce the
number of traces on a board, a different set of challenges arise when
designing these systems. This seminar provides useful guidelines and
techniques when designing a high-speed channel. The seminar will cover a
channel model case study that includes how to address the challenges of
designing at high data rates (BGA breakout, crosstalk, vias, DC block
capacitor, and an SMA connector). These challenges are tied in and are
implemented in a complete end-to-end channel simulation.
At this net seminar, you'll learn how to:
* Address high-speed channel design challenges
* Analyze modeled and simulated high-speed interconnects
* Employ a simulation environment for an end-to-end channel
Thanks
Salman
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