[SI-LIST] Fwd: Re: Re: SDRAM Routing Topology - Follow Up
- From: Kevin K <khai77069@xxxxxxxxx>
- To: Chris.Cheng@xxxxxxxxxxxx, "Moran, Brian P" <brian.p.moran@xxxxxxxxx>, weirsi@xxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Sun, 16 Jul 2006 19:22:01 -0700 (PDT)
By the way, I've tried daisy-chain routing on my
board. The longest address trace is 7.7 inches and
the longest data trace is 5.5 inches. They are long
and that's when I started thinking about T topology.
Thank you,
Kevin
Note: forwarded message attached.
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Date: Sun, 16 Jul 2006 18:54:40 -0700 (PDT)
From: Kevin K <khai77069@xxxxxxxxx>
Subject: Re: [SI-LIST] Re: SDRAM Routing Topology - Follow Up
To: Chris.Cheng@xxxxxxxxxxxx, "Moran, Brian P" <brian.p.moran@xxxxxxxxx>,
weirsi@xxxxxxxxxx, si-list@xxxxxxxxxxxxx
In-Reply-To: <DF089B15F863804D90ECE2E7ADFD35E701099CCB@xxxxxxxxxxxxxxxxxxxxxx>
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Chris,
Yes, I'm working on a PPC405EP based design that uses
four SDR SDRAM's running at 133MHz.
The clocks and DQM signals are T routed. My question
is which topology I should use for Addr/Control and DQ
signals?
You're correct. There're no DQS signals for SDR.
Does this mean DQ signals in SDR need to match length
with DQM signals???
I have done a few designs with DDR and DDR2 DIMM
sockets on the motherboard, but have not worked with
PPC and SDRAM on motherboard. Therefore, I'm not very
familiar with PPC and SDRAM. I would like to get
advices from designers who have used PPC or had
experiences with SDRAM on motherboard.
So far, I have received mixed responses. Some
engineers suggest T topology; others are against it.
Regards,
Kevin
--- Chris Cheng <Chris.Cheng@xxxxxxxxxxxx> wrote:
> I am sorry, are we talking about PPC405EP that uses
> x32 SDRAM, am I correct ?
> Why are we all the sudden talking about DQS as if we
> are designing DDR ?
> If the load is just 4 SDRAM (not DIMMs), at 133 or
> 100MHz, do we really care whether we route it as T
> or daisy chain ? Does that make any big differences
> with such small devices that can be placed closely
> together and at that speed (100MHz/133MHz) ?
> Finally, why do we need to daisy chain the clocks
> for SDRAMs ?
>
> ________________________________
>
> From: si-list-bounce@xxxxxxxxxxxxx on behalf of
> Kevin K
> Sent: Sat 7/15/2006 5:23 PM
> To: Moran, Brian P; weirsi@xxxxxxxxxx;
> si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: SDRAM Routing Topology -
> Follow Up
>
>
>
> Brian,
> I'm working with SDR SDRAM. The clocks and DQS
> signals are T routed. The signals I have questions
> on
> are Adddr/Control and DQ signals.
>
> Thank you,
> Kevin
>
>
> --- "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
> wrote:
>
> > Kevin,
> >
> > One thing I forgat to mention is if you are
> talking
> > about dasy chaining
> > CTRL and ADR/CMD,
> > you may be forced to dasiy chain CLK in order to
> > keep the setup and hold
> > timing in spec.
> > Can't say for sure becasue I have not ever tried
> it.
> > If you do daisy
> > chain CLK, then
> > you have all sorts of problems with the strobe to
> > CLK setup and hold
> > timing. So again,
> > my inclination would be the Tee topology.
> >
> >
> > Brian P. Moran
> > MPG Advanced Platform Engineering
> > Intel Corporation
> >
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > On Behalf Of Kevin K
> > Sent: Saturday, July 15, 2006 1:43 PM
> > To: weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: SDRAM Routing Topology
> >
> > Steve,
> > You're right.
> > The address and control lines go to all four
> > SDRAM's.
> > When I tried to use T topology, but it's very
> > difficult to length match
> > all four branches of the T.
> > I'm now trying daisy-chain topology, it's easier
> to
> > route and there're
> > not branches of the T to match, but the trace
> > lengths are longer than T
> > topology. I will have to run some simulations.
> > Which topology do most people use?
> > Has anybody had any timing issues with a design
> > using daisy-chain
> > topology (since the traces are long)?
> >
> > Thank you,
> > Kevin
> >
> > --- steve weir <weirsi@xxxxxxxxxx> wrote:
> >
> > > Kevin, it doesn't sound like you have a
> simulator.
> >
> > > A T topology will
> > > get into trouble pretty quickly I advise against
> > it.
> > > A simulator
> > > would tell you if you can get away with what you
> > would like.
> > >
> > > Steve
> > > At 07:34 AM 7/1/2006, Kevin K wrote:
> > > >Dear Experts,
> > > >I'm working on a design that uses the PPC405EP
> > > (Power
> > > >PC). The memory subsystem consists of four SDR
> > SDRAM's. What's the
> > > >SDRAM routing topology?
> > > >1) Daisy-chain topology
> > > >2) T-topology
> > > >3) Either topology as long as the length
> > > requirements
> > > >are met.
> > > >
> > > >I have a reference design board that uses both
> > daisy-chain topology
> > > >and T-topology.
> > > >
> > > >Thank you,
> > > >Kevin
> > > >
> > > >
> > >
> >
> >__________________________________________________
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