[SI-LIST] [Fwd: Re: Re: Reducing SSO noise in an FPGA]

From: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
To: "silist" <si-list@xxxxxxxxxxxxx>
Date: Fri, 11 Jul 2003 16:41:35 -0700
Hi, Scott,

We have been working with a big ASIC design company on IO-SSO problem. 
You are quite right - in order to perform an accurate IO SSO analysis, 
we need both on-chip P/G network, and the package data. We use our 
extraction tool to extract the on-chip P/G network, and the package is a 
166-port S-parameter network model, the whole netlist has roughly 2.5 
million RCLs, plus 50K mosfet transistors, and the big S-parameter 
network - all together to simulate more than 300 I/O SSO, and the result 
shows big vdd-drop, ground bounce, and huge current peaks. It's quite 
amazing to see all those effects, and running the simulation just on a 
Linux desktop.

Regards,

Yu
===

Scott McMorrow wrote:

>Bill,
>I respectfully disagree with you and agree with Chris.  The SSO problem 
>wrt. to a device driver is a chip and package problem.  The round trip 
>time from the driver, through the package and out to a BC layer is 
>longer than the risetime for almost all packages and devices where this 
>is a problem.  SSO is generally a loop inductance issue.  No amount of 
>capacitance at the end of a large loop inductance in a power delivery 
>system can effect the problem. For the capacitance to be effect, it has 
>to be in the package or on the die. As a result, the PCB has no effect 
>on instantaneous SSO problems.  You can make the problem worse, but if 
>the package and silicon are already hosed, their ain't much you can do 
>to make it better.  SSO problems are almost always I/O power issues.  
>This is a region of silicon and package design where there are many 
>tradeoffs, quite a few of them wrong.  If this portion of the design is 
>already broken (and it is in quite a few FPGA, ASICs and even in custom 
>devices) then all the BC in the world will not fix it.
>
>BC can deal with lower frequency noise components and lower the overall 
>noise floor for a PCB power delivery system.  BC can reduce the power 
>impedance profile. BC can even be used to change the resonant frequency 
>of a board, if the dielectric constant is higher than FR4.  But BC 
>cannot help the classical SSO problem.  If you have real engineering 
>data that shows differently, I would enjoy seeing it.
>
>best regards,
>
>scott
>



-- 
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com



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[SI-LIST] [Fwd: Re: Re: Reducing SSO noise in an FPGA]

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