[SI-LIST] Re: Fw: HELP LVDS LINE
- From: umashankar.subramaniam@xxxxxxxxxxxxxx
- To: steve weir <weirsi@xxxxxxxxxx>
- Date: Tue, 26 May 2009 15:31:22 +0530
please use this guidelines for your board which answers ur question 1,2
(See attached file: lvdsboardwp.pdf)
umashankar
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Senior Engineer - R&D, Drives & Power Systems,
Converteam EDC Pvt Ltd, Chennai
+91-44.6611.5418
steve weir
<weirsi@xxxxxxxxx
m> To
Sent by: david stern <dan1_st@xxxxxxxxx>
si-list-bounce@fr cc
eelists.org si-list <si-list@xxxxxxxxxxxxx>
Subject
[SI-LIST] Re: Fw: HELP LVDS LINE
05/25/2009 12:51
PM
David, there are multiple requirements:
* You will want to match the two signals in each pair at a minimum to
guarantee skew does not ever exceed Tr or Tf min.
* The match between any data pair and the clock pair must be close
enough to guarantee Tsu, and Th
Steve.
david stern wrote:
>
>
>
>
>
>
> Hello
> Ihave two questions that I need help:
>
> 1) I have 5 differential lines one of them is clock running at 60MHz.
> I am at the layout stage. the five pairs should be at the same length.
> But actually they don't have the same length. What is the maximum
difference in
> length that I can accept and how do I calculate it?
>
> 2) Those signals are deserialized into 28 lines. Are those lines should
be ROUTED with the same length? What is the maximum difference in
> length that I can accept and how do I calculate it?
>
> Thank you
>
> David
>
>
>
>
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