[SI-LIST] Fw: AC Common Mode Voltage

  • From: Joseph.Schachner@xxxxxxxxxxxxxxxxxx
  • To: si-list@xxxxxxxxxxxxx
  • Date: Thu, 7 May 2015 09:28:13 -0400

If the measurement is at full bandwidth then the main thing that affects
it is timing skew between the two sides of a (supposed to be) differential
signal.
If the two sides are synchronized, then when one goes up the other goes
down at exactly the same time, with the same transition time. If you add
the two sides of a perfect differential pair you should get a flat line.
You can scale it correctly by dividing by 2. Then the flat line will be
at the center voltage of each side.

If the two sides are NOT synchronized, say by 1/4 of a UI (that's a lot),
then one side goes up and gets almost all the way up before the other side
goes down. If you add the two sides of this signal you would get a line
with positive and negative spikes that, peak to peak, are nearly the full
swing of the signal.

If the measurement is very low bandwidth then this may not be the primary
cause. But if it is full bandwidth (I'll bet it is) then skew between the
sides of what should be a diff pair is a critical factor. This can only
be fixed by fixing the layout.

If falling edge is much faster than rising edge, that can also cause
common mode spikes. Common mode is just what you see when you add the two
sides of a differential pair of signals (and divide by 2 for scaling). It
should be nothing.

---- Joe S.



From: mo han <hanmoggq@xxxxxxxxx>
To: si-list@xxxxxxxxxxxxx,
Date: 05/07/2015 06:48 AM
Subject: [SI-LIST] AC Common Mode Voltage
Sent by: si-list-bounce@xxxxxxxxxxxxx



Hi experts:
I am test the SI for USB 3.0, the ac common mode voltage has some
problems,
what is ac common mode voltage and what factors affect it ?
Thanks
Mo Han


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  • » [SI-LIST] Fw: AC Common Mode Voltage - Joseph . Schachner