[SI-LIST] Re: Free, hands-on PCIe Workshop: Signal Integrity Design, Analysis, and Verification
- From: <colin_warwick@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 24 Jul 2008 15:10:47 -0600
Well, I'm not have much luck with URLs and SI-List today :-(
Try this one:
http://tinyurl.com/69snau
If anyone knows why the listserv is mangling my links (and what to do =
about it), please post.
-----Original Message-----
From: Jitesh Shah [mailto:jeetshah@xxxxxxxxx]=20
Sent: Thursday, July 24, 2008 4:13 PM
To: WARWICK,COLIN (A-Americas,ex1)
Subject: Re: [SI-LIST] Free, hands-on PCIe Workshop: Signal Integrity =
Design, Analysis, and Verification
Hi Colin,
The link does not work. Can you guide me to the correct link.
Thanks,
Jitesh Shah
IDT
--- On Thu, 7/24/08, colin_warwick@xxxxxxxxxxx =
<colin_warwick@xxxxxxxxxxx> wrote:
> From: colin_warwick@xxxxxxxxxxx <colin_warwick@xxxxxxxxxxx>
> Subject: [SI-LIST] Free, hands-on PCIe Workshop: Signal Integrity =
Design, Analysis, and Verification
> To: si-list@xxxxxxxxxxxxx
> Date: Thursday, July 24, 2008, 12:50 PM
> Dear All,
> We (Agilent EEsof EDA) are offering a free, hands-on PCIe
> Workshop in =3D
> several US cities in July and August. Please register if
> you have an =3D
> interest.
> Thanks!
> -- Colin Warwick
> Signal Integrity Product Manager
> Agilent EEsof EDA
> Overview:
> At multigigabit per second data rates and with channel
> flight times =3D
> longer than a bit period, signal integrity is a major
> concern. Under =3D
> these conditions, high-speed analog effects, previously
> only seen in =3D
> high frequency RF and microwave engineering, can impair the
> signal =3D
> quality and degrade the bit error rate of the link. This
> hands-on =3D
> workshop will show you how use Advanced Design System (ADS)
> to =3D
> dramatically reduced product design cycles by resolving
> these issues =3D
> early in the design cycle.
>=20
> Using PCI Express serial link as an example, we'll
> illustrate how you =3D
> can:
> * Analyze complete serial links by co-simulating individual
> components, =3D
> each at its most appropriate level of abstraction: link-,
> circuit- or =3D
> physical-level.=3D20
> * Import S-parameter backplane and interconnect models
> accurately into =3D
> transient (SPICE) simulations.=3D20
> * Perform jitter diagnosis with the proven EZJIT Plus
> algorithm used in =3D
> Agilent instruments.
> Dates - Cities:
> July 29 - Austin, TX=3D20
> July 30 - Richardson, TX=3D20
> July 31 - Santa Clara, CA=3D20
> August 5 - Allentown, PA=3D20
> August 5 - Andover, MA=3D20
> August 7 - Cary, NC=3D20
> August 14 - Naperville, IL=3D20
> August 18 - Chandler, AZ=3D20
> August 20 - Loveland, CO
> Agenda:
> 9:30 - 10:00 - Registration and Continental Breakfast=3D20
> 10:00 - 12:00 - Hands-on workshop: Signal Integrity Design,
> Analysis and =3D
> Verification=3D20
> 12:00 - 1:00 - Lunch=3D20
> 1:00 - 3:00 - Workshop continued=3D20
> Registration: =3D
> http://www.distributech.ca/agilent2/registration.asp?seminarid=3D3D193
> .
>=20
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