[SI-LIST] Re: FW: Power plane / VCC plane as reference for differential
- From: "Chris Chalmers" <cchalmers@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 23 Aug 2004 08:35:59 +0100
Senthill,
As steve says I think its a very bad idea. From your
mail I think you are cutting the reference plane
between the pairs in order to stop the uturn and
the return current loop from radiating. Bad news
it will get worse. The return current will find another
way home (the path of least inductance). The path maybe
longer and contain more parastics (capacitor inductance).
Its bad enough having a void. Its worse making two to fix
one.
Chris
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Senthil Velmurugan
Sent: 21 August 2004 00:13
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] FW: Power plane / VCC plane as reference for
differential
Hi Chris,
Thanks for the link on the Uturn current.
Since Nikki has two VCC power planes. Can we minimize/avoid the effect
of U-turns by slicing=20
a portion of reference plane(wedge) just between the diff pairs and
having decaps for those power plans near the trace and void(GND
transition caps) this way there is no R-dash +/- currents we see R+/-
currents from TXr to Rxr. I anticipate R+/- to go from Vccplane1 to GND
through cap then from GND to VCC plane2.=20
I hope we have enough space between the pair so the individual trace
impedance is not affected w.r.t to it's reference.
Thanks
Senthil
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