My experience... usually stuck with using magnetics to couple since many card
vendors use them (so they can go internal or external). Prefer to use
1000base-kx if possible. Never had SI or EMI problems in dozens of
applications. -KX is fairly low edge-rate.
Mike
________________________________________
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> on behalf of
Sanjeev Gupta <sanjeev@xxxxxxxxxxxxxxxxxxxxxxxxxx>
Sent: Monday, July 4, 2016 8:44 AM
To: binayaks@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Ethernet 1000 Base-T over backplane
Binayaka,
Your problem statement is not very clear. are you seeing hordes of SI
issue in real PCB? or you are just afraid of too many potential SI issues
in your design.
Your worry about return current path may not be true. How do you know
whether signal will take digital ground or chassis ground? Have you done
any simulation to see exact return current?. Most of the return current
worries are just hypothesis. Overall, high frequency signal return current
will follow the path of least inductance. But other parameter such as type
of signalling, frequency components, switching pattern, device capacitance
are also important in return current path. your need to apply all such
factors in your layout and see the problem. Efficient decoupling scheme can
surely resolve all such worries. Each decoupling capacitor value and their
location is also very significant to return path current.
Regarding EMI concerns:
use of common-mode choke or ferrite bead to reduce EMI issue is well
suggested solution by the experts. Kindly make proper selection of such
components and account all parasitic of such component in the design. if
selection is not proper, use of such components can even increase the level
of your problems. There was one discussion on si-list some time back
about 'use of ferrite bead in resolving power integrity noise issues'. Many
people reported negative impact of ferrite bead in resolving power plane
noise issues. So kindly give all such thoughts on any problem.
Signal integrity does not follow any *golden rule* for any design. There
could be plenty of methods to achieve same design goals.. There are only *basic
rules* as suggest & written by many SI experts.
Thanks & Regards
Sanjeev Gupta
www.sigintegrity-solutions.com
On Mon, Jul 4, 2016 at 1:50 PM, Binayak Shrestha <binayaks@xxxxxxxxx> wrote:
Hi everyone,
I would like to send Ethernet data at 1.25 Gb/s from one daughter card to
another over a backplane. The standard to use is 1000 Base-KX. This spec
clearly states to use ac-coupling capacitors at the receiver side of the
differential pair.
I have seen many old boards using Ethernet 1000 Base-T copper phys to do
the same thing. This is what they generally do: In the daughter cards, they
use discrete magnetics (the isolation transformer followed by common mode
choke). The transformer side, connecting to the backplane, is given chassis
ground while the other side of the transformer connected to signal return
(digital ground). Then, all the ground pins of the connector are connected
to chassis ground, both on daughter card and backplane. For this they split
the ground plane in the digital card to create chassis ground plane. Same
is done at the other daughter card too.
As far as I know, the common mode choke is used to attenuate the common
currents in differential signal from reaching the twisted pair cable like a
CAT5 cable to reduce EMI. Similarly, the ground is split as in RJ45
connector to connect the signal return plane for differential signal (after
transformer) to chassis for making a better Faraday cage. Both these
requirements are not required for data transfer over backplane.
My doubt is:
1) Is it correct use 1000 base-T copper phy in backplane? Moreover using
in the way described above? I’m seeing hordes of SI issues – taking chassis
ground as a signal return plane in backplane, unnecessarily adding
magnetics in the serial path of the differential lines, etc. I think they
will all lead to performance degradation.
Regards,
Binayak
--
Binayak Shrestha
Senior
Research Engineer,
C-DOT Centre for Development of Telematics
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