[SI-LIST] Errors with Capacitor EDA Models due to Oversimplification, Temperature, and DC Bias - Webinar
- From: "Allen Mayar/EXTON/USA/SALES/KEMET/US" <allenmayar@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 14 Oct 2009 09:20:10 -0400
Free webinar from Cadence and KEMET, click below to join
http://www.secure-register.net/cadence.php?product0
October 14, 2009 - Webinar At your Desktop, : 10:30 AM - 11:45 AM Pacific
Kind Regards
Allen Mayar
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