We have an employment opportunity in the Oracle SPARC Processor Group for *new* M.S. or Ph.D. graduates who have coursework and/or a research background in communication channel analysis and high-speed signaling. The work location is Burlington, MA. Please find the job description below. Please email me directly at jason.miller@xxxxxxxxxxx ------------------------------------------------------------------------------------------------------------------------------------ Description You will be responsible for simulating, modeling and designing serdes front-end interfaces including on-chip parasitics. As part of this effort you will develop electrical models of RF passives and packages using electromagnetic simulation tools. The work will include validating these electrical models through detailed simulation and measurement correlation work. You will also perform high-speed channel simulations, design test boards and make test board measurements using VNA. Job Requirements MS or Ph.D. in electrical engineering. Familiarity with Agilent ADS, Matlab and Spice. Experience with electromagnetic simulation tools such as Ansoft HFSS. Knowledge of high-frequency VNA measurement techniques is a big plus. Candidate will be proactive, curious, with strong written and oral communication skills and able to take projects to completion with some supervision. ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu