[SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents
- From: steve weir <weirsi@xxxxxxxxxx>
- To: alexh1@xxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Thu, 16 Feb 2006 12:51:08 -0800
Alex, this is going to be one of those infamous "it depends"
answers. If you have edges that are not too fast, and not too many
signals plowing through your stack-up, then the total amount of
energy that you are trying to couple through the cavity is
small. Lee just did a report on this using a single signal test
vehicle in his newsletter. You can buy a copy from his Speeding Edge web site.
At relatively fast edge rates, there is energy getting pumped into
the cavity, and as the edge rate gets steeper, or the cavity higher
this becomes more pronounced. Consider that to remain quasi-static,
we can only depend on a working radius that is a small fraction of
the rise time. That radius shrinks as the square root of Er, but
will be offset by the capacitance rising as Er. So Er cancels
out. I think this was also mentioned in one of this year's DC
papers, maybe the Weds paper on embedded capacitors.
The working radius also shrinks linearly with the rise time, making
the working capacitance vary as 1/(Tr^2), but the impedance at the
knee frequency only falls as 1/Tr. So, the effective impedance for a
fixed height cavity with no stitching, and no bypass capacitors goes
up as 1/Tr. The capacitance of a given cylinder also varies
inversely as the height. So, we can see that the effective impedance
the cavity presents is:
Zcavity = K * Height / Tr
With some combination of Height/Tr the discontinuity will be enough
to distort the signal. But long before that, it becomes a source of
energy for EMI and then victim cross talk.
But it is only an extraordinary cavity that does not have a pretty
high density of GND - GND stitch vias courtesy of the bypass
capacitors and ICs. Unfortunately, to the extent that they connect
to surface components and/or features, they also present a source of
CM currents. These vias provide wave guide edges through the cavity
from the nearest ground plane from the original image plane at the
start to the nearest ground plane to the next image plane. So,
supposing that we referenced 2.5 V starting and 1.8V ending, these
stitches would work in parallel with the cavity displacement currents
from the first to the last cavity. Depending on how far away those
vias are they work to reduce the effective height of the cavity.
Now, for the crucial question: Is this enough? And that is where
the "it depends" answer comes from. Certainly, if you have only one
or a few signals here or there that you have to do this with a dB or
so isn't going to cause a signaling problem, is unlikely to add up to
enough energy to become a cross talk problem, and depending on the
overall shielding strategy may be undetectable for EMC purposes. You
can see strong evidence of the first two in Lee's TDR
plots. However, if you were to take a big wide bus with fast edge
rates, like a 144 bit memory data bus and route it this way, all
those little half, or one dBs suddenly become a lot of total power
and the world becomes a very different and potentially troublesome place.
Given the possibilities a hierarchy of routing PREFERENCE for high
performance and low EMI has been documented in one variation or
another by a number of authors:
Best, route without any layer transitions.
Route from one side of an image plane to the other with appropriately
sized anti-pads.
Route from one image plane to another that are at the same DC
potential and bound together with a good density of stitch vias.
Route from one image plane on a DC voltage to one that is stitched
gnd, or vice-versa.
Worst route from one image plane to another that are two DC voltages
each occupying just one plane in the stack-up.
If you need to know the answer for a particular situation, then you
need a model, or physical analog.
Regards,
Steve.
At 11:45 AM 2/16/2006, Alex Horvath wrote:
>Normally, when I design a multi layer stackup I always try to
>alternate and pair Pwr-Gnd planes to maximize inter-plane
>capacitance. For example, a 16 layer stackup might look like-
>
>
> Sig - - - - - - -
> Gnd --------------
> Pwr --------------
> Sig - - - - - - - -
> Sig - - - - - - - -
> Gnd --------------
> Pwr --------------
> Sig - - - - - - - -
> Sig - - - - - - - -
> Gnd --------------
> Pwr --------------
> Sig - - - - - - - -
> Sig - - - - - - - -
> Gnd---------------
> Pwr ---------------
> Sig - - - - - - -
>
> For cost reasons I might be forced into a stackup with the same
> number of signal layers but with 2 power planes removed (14 layers,
> same dielectric thickness) -
>
> Sig - - - - - - -
> Gnd --------------
> Pwr --------------
> Sig - - - - - - - -
> Sig - - - - - - - -
> Gnd --------------
> Sig - - - - - - - -
> Sig - - - - - - - -
> Gnd --------------
> Sig - - - - - - - -
> Sig - - - - - - - -
> Gnd---------------
> Pwr ---------------
> Sig - - - - - - -
>
>
> Let's assume a signal traverses from the top signal layer to the
> bottom layer in both stackups. Let us also assume as a worst case
> that there are no nearby vias or decoup caps and the signal edge
> rate is approximately 10 times the via length (about 200 psec). Is
> there a significant difference in the expected signal quality when
> comparing these 2 stackups?
>
> My gut feel is that all else being equal the primary factor
> determining signal quality is the spacing of the planes. The DC
> assignment of the planes has (again ignoring effect of gnd or pwr
> vias) little effect and thus the signal quality in the above cases
> would be virtually identical.
>
> Since I hate to bet my designs on a gut feel hopefully someone
> can confirm or deny my assumptions.
>
>
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