Hi Hung,
In general, the PCIe G3 base specification defines the channel requirements
in section 4.3.6.4. Here, you will find a link to an open-source channel
modeling tool, Seasim. I have the link below for your reference. The
download for this tool contains a setup file for PCIe G3. Use the setup
file I mentioned to setup the tool for PCIe G3 analysis, add your channel
model in the touchstone file area, run the tool, and compare the output of
the tool to Table 4-27 per section 4.3.6.5.4.
http://www.pcisig.com/specifications/pciexpress/base2/seasim_package/.
It may be a typo, but you need a package on both the near and far side of
your model along with the PCB hosting the receiver. You may already have
this, but you may also want to consider adding the connector footprints to
your model as well.
*From your email:*
*PCIE_TX(AMI-IBIS model)--> Package --> Model board --> Cable and Connector
--> Backplane--> Connector (Probe Point)--> PCIE_RX(AMI-IBIS model) *
May I suggest you change it to:
Package --> Model board --> footprint --> Cable and Connector --> footprint
--> Backplane--> --> footprint --> Connector (Probe Point)--> footprint -->
PCB --> Package
Good luck,
Jason
Employed by and affiliated with Amphenol AICC (https://www.amphenol-icc.com/
)
On Sat, May 12, 2018 at 11:38 AM, Jeff Smith <jsmith@xxxxxxxxxxxxxxx> wrote:
Hi Hung,
If you have HyperLynx it has compliance tests built into it for PCIe
channels, you will need the S-parameters of the full channel but it
sounds like you already have that. I think Mentor has a video on
their web site that shows how to run the compliance test for a PCIe
channel.
Best Regards,
Jeff Smith
GHz Systems Inc.
858-829-9702
----- Original Message -----
From: hndang@xxxxxxxxxxxxxxxxxxx
To:"si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Cc:
Sent:Sat, 12 May 2018 13:54:46 +0000
Subject:[SI-LIST] EYE mask for SerDes Simulation
Dear Experts,
I use SystemSI to run AMI-IBIS analysis for PCIE3.0 and SATA3.0.
I have concern about EYE mask to check the simulation results.
The channel is configured below:
PCIE_TX(AMI-IBIS model)--> Package --> Model board --> Cable and
Connector --> Backplane--> Connector (Probe Point)--> PCIE_RX(AMI-IBIS
model)
Per my understand, to determine PASS or FAIL result, It need the EYE
mask requirement at receiver. But I lack AMI-IBIS model at receiver
side.
I have replaced by AMI-IBIS model of our chip. The purpose is to make
termination for probe point.
Now, I can probe the EYE diagram before it's send to AMI-IBIS model.
My question is how to know the channel meet PCIE3.0 or SATA3.0
specification?
In the PCIE3.0 spec, the EYE mask requires 35mV EYE height and 0.3UI
EYE width. But signal is measured after it's processed by
CTLE/DFE/CDR.
In the SATA3.0 spec, I cannot find EYE mask requirement.
Thanks.
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